Data Sheet

PCIe Programming Interface—Ethernet Controller I210
617
9.5.1.4 Uncorrectable Error Severity (0x10C; RWS)
The Uncorrectable Error Severity register controls whether an individual uncorrectable error is reported
as a fatal error. An uncorrectable error is reported as fatal when the corresponding error bit in the
severity register is set. If the bit is cleared, the corresponding error is considered non-fatal.
17 RWS 0b Receiver Overflow Mask
18 RWS 0b Malformed TLP Mask
19 RWS 0b ECRC Error Mask
20 RWS 0b Unsupported Request Error Mask
21 RO 0b
ACS Violation Mask
Not supported in the I210.
22 RO 0b
Uncorrectable Internal Error Mask (Optional)
Not supported in the I210.
23 RO 0b
MC Blocked TLP Mask (Optional)
Not supported in the I210.
24 RO 0b
AtomicOps Egress Blocked Mask (Optional)
Not supported in the I210.
25 RO 0b
TLP Prefix Blocked Error Mask (Optional)
Not supported in the I210.
31:26 RO 0x0 Reserved
Bit
Location
Attribute
Default
Value
Description
3:0 RO 0001b Reserved
4 RWS 1b Data Link Protocol Error Severity
5RO1b
Surprise Down Error Severity (Optional)
Not supported in the I210.
11:6 RO 0x0 Reserved
12 RWS 0b Poisoned TLP Severity
13 RWS 1b Flow Control Protocol Error Severity
14 RWS 0b Completion Timeout Severity
15 RWS 0b Completer Abort Severity
16 RWS 0b Unexpected Completion Severity
17 RWS 1b Receiver Overflow Severity
18 RWS 1b Malformed TLP Severity
19 RWS 0b ECRC Error Severity
20 RWS 0b Unsupported Request Error Severity
21 RO 0b
ACS Violation Severity
Not supported in the I210.
22 RO 1b
Uncorrectable Internal Error Severity (Optional)
Not supported in the I210.
23 RO 0b
MC Blocked TLP Severity (Optional)
Not supported in the I210.
Bit
Location
Attribute
Default
Value
Description