Data Sheet

Ethernet Controller I210 —PCIe Programming Interface
616
9.5.1.3 Uncorrectable Error Mask (0x108; RWS)
The Uncorrectable Error Mask register controls reporting of individual uncorrectable errors by device to
the host bridge via a PCIe error message. A masked error (respective bit set in mask register) is not
reported to the host bridge by an individual device. There is a mask bit per bit in the Uncorrectable
Error Status register.
Bit
Location
Attribute
Default
Value
Description
3:0 RO 0x0 Reserved
4 R/W1CS 0b Data Link Protocol Error Status
5RO0b
Surprise Down Error Status (Optional)
Not supported in the I210.
11:6 RO 0x0 Reserved
12 R/W1CS 0b Poisoned TLP Status
13 R/W1CS 0b Flow Control Protocol Error Status
14 R/W1CS 0b Completion Timeout Status
15 R/W1CS 0b Completer Abort Status
16 R/W1CS 0b Unexpected Completion Status
17 R/W1CS 0b Receiver Overflow Status
18 R/W1CS 0b Malformed TLP Status
19 R/W1CS 0b ECRC Error Status
20 R/W1CS 0b Unsupported Request Error Status
21 RO 0b
ACS Violation Status
Not supported in the I210.
22 RO 0b
Uncorrectable Internal Error Status (Optional)
Not supported in the I210.
23 RO 0b
MC Blocked TLP Status (Optional)
Not supported in the I210.
24 RO 0b
AtomicOps Egress Blocked Status (Optional)
Not supported in the I210.
25 RO 0b
TLP Prefix Blocked Error Status (Optional)
Not supported in the I210.
31:26 RO 0x0 Reserved
Bit
Location
Attribute
Default
Value
Description
3:0 RO 0x0 Reserved
4 RWS 0b Data Link Protocol Error Mask
5RO0b
Surprise Down Error Mask (Optional)
Not supported in the I210.
11:6 RO 0x0 Reserved
12 RWS 0b Poisoned TLP Mask
13 RWS 0b Flow Control Protocol Error Mask
14 RWS 0b Completion Timeout Mask
15 RWS 0b Completer Abort Mask
16 RWS 0b Unexpected Completion Mask