Data Sheet

Ethernet Controller I210 —PCIe Programming Interface
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9.4.6.14 Link Status 2 (0xD2; RW)
9.5 PCIe Extended Configuration Space
PCIe extended configuration space is located in a flat memory-mapped address space. PCIe extends
the configuration space beyond the 256 bytes available for PCI to 4096 bytes. The I210 decodes an
additional 4-bits (bits 27:24) to provide the additional configuration space as shown in Table 9-9. PCIe
reserves the remaining 4 bits (bits 31:28) for future expansion of the configuration space beyond 4096
bytes.
The configuration address for a PCIe device is computed using a PCI-compatible bus, device, and
function numbers as follows.
PCIe extended configuration space is allocated using a linked list of optional or required PCIe extended
capabilities following a format resembling PCI capability structures. The first PCIe extended capability is
located at offset 0x100 in the device configuration space. The first Dword of the capability structure
identifies the capability/version and points to the next capability.
The I210 supports the following PCIe extended capabilities.
11 RWS 0b
Compliance SOS
When set to 1b, the LTSSM is required to send SOS periodically in between the (modified)
compliance patterns.
12 RWS 0b
Compliance De-emphasis
This bit sets the de-emphasis level in Polling.Compliance state if the entry occurred due to
the Enter Compliance bit being 1b.
Encodings:
1b -3.5 dB
0b -6 dB
When the Link is operating at 2.5 GT/s, the setting of this bit has no effect.
15:13 RO 0x0 Reserved
Bits R/W Default Description
0RO0b
Current De-emphasis Level – When the Link is operating at 5 GT/s speed, this bit reflects
the level of de-emphasis. it is undefined when the Link is operating at 2.5 GT/s speed
Encodings:
1b -3.5 dB
0b -6 dB
15:1 RO 0x0 Reserved
Table 9-9. PCIe Extended Configuration Space
31 28 27 20 19 15 14 12 11 2 1 0
0000b Bus # Device # Fun # Register Address (offset) 00b
Bits R/W Default Description