Data Sheet

Interconnects—Ethernet Controller I210
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The I210 controls accesses to the Flash when it decodes a valid access. Attempts to out-of-range write
access the PCIe Expansion/Option ROM module (beyond the provisioned 512 KB) is silently ignored,
while read access might return any value. The same is done for out-of-range accesses to the host
memory BAR.
Notes: The I210 supports four byte writes to the Flash. Byte Enable (BE) pins can be set in a
consecutive way (starting from 0) for writing less than four bytes.
Flash read accesses are assembled by the I210 each time the access is greater than a byte-
wide access.
Flash read access times is in the order of 2 s (depending on Flash specification). The device
continues to issue retry accesses during this time.
Flash write access times can be in the order of 2 s to 200 s (depending on Flash
specification). Following a write access to the Flash, software should avoid initiating any read
or write access to the device until the Flash write access completes.
While in the non-secure mode, Flash BAR access while FLA.FL_REQ is asserted (and granted) is
forbidden. It can lead to a PCIe hang as a bit-banging access requires several PCIe accesses.Figure 3-4
and Figure 3-5 show the BARs mapping schemes according to the size of the BAR vs. the Flash memory
sizes supported.