Data Sheet

Ethernet Controller I210 —PCIe Programming Interface
610
9.4.6.9 Link Status (0xB2; RO)
This register provides information about PCIe link specific parameters. This is a read only register.
9.4.6.10 Reserved (0xB4-0xC0; RO)
Unimplemented reserved registers not relevant to PCIe endpoint.
The following registers are supported only if the capability version is two and above.
9.4.6.11 Device Capabilities 2 (0xC4; RO)
This register identifies PCIe device specific capabilities.
10 RO 0b
Link Bandwidth Management Interrupt Enable
Not supported in the I210. RO as zero.
11 RO 0b
Link Autonomous Bandwidth Interrupt Enable
Not supported in the I210. RO as zero.
15:12 RO 0000b Reserved
Bits R/W Default Description
3:0 RO 0001b
Link Speed
This field indicates the negotiated link speed of the given PCIe link.
Defined encodings are:
0001b = 2.5 Gb/s PCIe link.
0010b = Not supported (5 Gb/s PCIe link).
All other encodings are reserved.
9:4 RO 000001b
Negotiated Link Width
Indicates the negotiated width of the link.
Relevant encoding for the I210 are:
000001b = x1
000010b = Not supported (x2)
000100b = Not supported (x4)
10 RO 0b Reserved (was: Link Training Error)
11 RO 0b
Link Training
Indicates that link training is in progress.
12 HwInit 1b
Slot Clock Configuration
When set, indicates that the I210 uses the physical reference clock that the platform provides
on the connector. This bit must be cleared if the I210 uses an independent clock. The Slot
Clock Configuration bit is loaded from the Slot_Clock_Cfg bit in PCIe Init Configuration 3 Word
(Word 0x1A) Flash word.
13 RO 0b
Data Link Layer Link Active
Not supported in the I210. RO as zero.
14 RO 0b
Link Bandwidth Management Status
Not supported in the I210. RO as zero.
15 RO 0b Reserved
Bits R/W Default Description