Data Sheet

PCIe Programming Interface—Ethernet Controller I210
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9.4.6.8 Link Control Register (0xB0; RO)
This register controls PCIe link specific parameters.
21 RO 0b
Link Bandwidth Notification Capability Status
Not supported in the I210. RO as zero.
22 RO 1b
ASPM Optionality Compliance
Software is permitted to use the value of this bit to help determine whether to
enable ASPM or whether to run ASPM compliance tests.
23 RO 00b Reserved
31:24 HwInit 0x0
Port Number
The PCIe port number for the given PCIe link. Field is set in the link training phase.
Bits R/W Default Description
1:0 RW 00b
Active State Power Management (ASPM) Control – This field controls the level of Active
State Power Management (ASPM) supported on the I210 PCI Express Link.
Defined encodings are:
00b = PM disabled.
01b = L0s entry supported.
10b = L1 Entry Enabled.
11b = L0s and L1 supported.
Note: “L0s Entry Enabled” enables the Transmitter to enter L0s is supported. If L0s is
supported, the Receiver must be capable of entering L0s even when the
Transmitter is disabled from entering L0s (00b or 10b).
According to PCIe spec, this field shall not be reset on FLR.
2 RO 0b Reserved
3RW0b
Read Completion Boundary
Read Completion Boundary (RCB) – Optionally Set by configuration software to indicate the
RCB value of the Root Port Upstream from the Endpoint or Bridge.
Defined encodings are:
0b = 64 byte
1b = 128 byte
Configuration software must only Set this bit if the Root Port Upstream from the Endpoint
or Bridge reports an RCB value of 128 bytes (a value of 1b in the Read Completion
Boundary bit).
4RO0b
Link Disable
Not applicable for endpoint devices; hardwired to 0b.
5RO0b
Retrain Clock
Not applicable for endpoint devices; hardwired to 0b.
6RW0b
Common Clock Configuration
When this bit is set, it indicates that the I210 and the component at the other end of the
link are operating with a common reference clock. A value of 0b indicates that both operate
with an asynchronous clock. This parameter affects the L0s exit latencies.
Note: According to PCIe spec, this field shall not be reset on FLR.
7RW0b
Extended Synch
When this bit is set, it forces an extended Tx of a FTS ordered set in FTS and an extra TS1
at exit from L0s prior to enter L0.
Note: According to PCIe spec, this field shall not be reset on FLR.
8RO0b
Enable Clock Power Management
Not supported in the I210. RO as zero.
9RO0b
Hardware Autonomous Width Disable
Not supported in the I210. RO as zero.
Bits Rd/Wr Default Description