Data Sheet

PCIe Programming Interface—Ethernet Controller I210
605
9.4.6.3 PCIe CAP (0xA2; RO)
The PCIe capabilities register identifies the PCIe device type and associated capabilities. This is a read
only register.
9.4.6.4 Device Capabilities (0xA4; RO)
This register identifies the PCIe device specific capabilities. It is a read only register.
Bits Default R/W Description
3:0 0010b RO
Capability Version
Indicates the PCIe capability structure version number. The I210 supports both version
1 and version 2 as loaded from the PCIe Capability Version bit in the Flash.
7:4 0000b RO
Device/Port Type
Indicates the type of PCIe function. a native PCI function with a value of 0000b.
80bRO
Slot Implemented
The I210 does not implement slot options therefore this field is hardwired to 0b.
13:9 00000b RO
Interrupt Message Number
The I210 does not implement multiple MSI interrupts, therefore this field is hardwired
to 0x0.
15:14 00b RO Reserved
Bits R/W Default Description
2:0 RO 010b
Max Payload Size Supported
This field indicates the maximum payload that the I210 can support for TLPs. It is loaded from
the Flash’s PCIe Init Configuration 3 word, 0x1A (with a default value of 512 bytes. See
Section 6.2.16).
4:3 RO 00b
Phantom Function Supported
Not supported by the I210.
5RO0b
Extended Tag Field Supported
Max supported size of the Tag field. The I210 supported 5-bit Tag field.
8:6 RO 011b
Endpoint L0s Acceptable Latency
This field indicates the acceptable latency that the I210 can withstand due to the transition
from the L0s state to the L0 state. value loaded from the Flash PCIe Init Configuration 1 word,
0x18 (See Section 6.2.14).
11:9 RO 110b
Endpoint L1 Acceptable Latency
This field indicates the acceptable latency that the I210 can withstand due to the transition
from the L1 state to the L0 state. value loaded from the Flash PCIe L1 Exit latencies word,
0x14 (See Section 6.2.11).
12 RO 0b
Attention Button Present
Hardwired in the I210 to 0b.
13 RO 0b
Attention Indicator Present
Hardwired in the I210 to 0b.
14 RO 0b
Power Indicator Present
Hardwired in the I210 to 0b.
15 RO 1b
Role-Based Error Reporting
This bit, when set, indicates that the I210 implements the functionality originally defined in the
Error Reporting ECN for PCIe Base Specification 1.0a and later incorporated into PCIe Base
Specification 1.1. Set to 1b in the I210.
17:16 RO 000b Reserved
25:18 RO 0x00
Slot Power Limit Value
Hardwired in the I210 to 0x00, as the I210 consumes less than the 25 W allowed for its form
factor.