Data Sheet

Ethernet Controller I210 —PCIe Programming Interface
604
9.4.5.4 VPD Data (0xE4; RW)
This register contains the VPD read/write data.
9.4.6 PCIe Configuration Registers
PCIe provides two mechanisms to support native features:
• PCIe defines a PCI capability pointer indicating support for PCIe.
• PCIe extends the configuration space beyond the 256 bytes available for PCI to 4096 bytes.
The I210 implements the PCIe capability structure for endpoint devices as follows:
9.4.6.1 Capability ID (0xA0; RO)
This field equals 0x10 indicating the linked list item as being the PCIe Capabilities registers.
9.4.6.2 Next Pointer (0xA1; RO)
Offset to the next capability item in the capability list. Its value of 0xE0 points to the VPD structure. If
VPD is disabled, or operating in mode, a value of 0x00 value indicates that it is the last item in the
capability-linked list.
Bits Default R/W Description
31:0 X RW
VPD Data
VPD data can be read or written through this register. The LSB of this register (at offset four in
this capability structure) corresponds to the byte of VPD at the address specified by the VPD
Address register. The data read from or written to this register uses the normal PCI byte
transfer capabilities. Four bytes are always transferred between this register and the VPD
storage component. Reading or writing data outside of the VPD space in the storage
component is not allowed.
In a write access, the data should be set before the address and the flag is set.
Byte Offset Byte 3 Byte 2 Byte 1 Byte 0
0xA0 PCI Express Capability Register (0x0002)
Next Pointer (0xE0/
0x00)
Capability ID (0x10)
0xA4 Device Capability
0xA8 Device Status Device Control
0xAC Link Capabilities
0xB0 Link Status Link Control
0xB4 Reserved
0xB8 Reserved Reserved
0xBC Reserved
0xC0 Reserved Reserved
0xC4 Device Capabilities 2
0xC8 Reserved Device Control 2
0xCC Reserved
0xD0 Link Status 2 Link Control 2
0xD4 Reserved
0xD8 Reserved Reserved