Data Sheet

Ethernet Controller I210 —PCIe Programming Interface
602
9.4.3.4 MSI-X Table Offset (0x74; R/W)
9.4.3.5 MSI-X Pending Bit Array - PBA Offset (0x78; R/W)
9.4.4 CSR Access Via Configuration Address Space
9.4.4.1 IOADDR Register (0x98; R/W)
This is a read/write register. Register is cleared at Power-up or PCIe reset.
Note: When function is in D3 state Software should not attempt to access CSRs via the IOADDR and
IODATA registers.
Bits Default Type Description
31:3 0x000 RO
Table Offset
Used as an offset from the address contained by one of the function’s BARs to point to the base
of the MSI-X table. The lower three table BIR bits are masked off (set to zero) by software to
form a 32-bit Qword-aligned offset.
2:0 0x3/0x4 RO
Tab le BIR
Indicates which one of a function’s BARs, located beginning at 0x10 in configuration space, is
used to map the function’s MSI-X table into memory space.
BIR values: 0...5 correspond to BARs 0x10…0x 24 respectively. A BIR value of 3 indicates that
the table is mapped in BAR 3 (address 0x1C).
When BARCTRL.BAR32 equals 0b (64 bit MMIO mapping) the table BIR equals 0x4. When
BARCTRL.BAR32 equals 1b (32 bit MMIO mapping) the table BIR equals 0x3.
Bits Default Type Description
31:3 0x400 RO
PBA Offset
Used as an offset from the address contained by one of the function’s BARs to point to the base
of the MSI-X PBA. The lower three PBA BIR bits are masked off (set to zero) by software to
form a 32-bit Qword-aligned offset.
2:0 0x3 RO
PBA BIR: Indicates which one of a function’s Base Address registers, located beginning at 10h
in Configuration Space, is used to map the function’s MSI-X PBA into Memory Space.
BIR values: 0...5 correspond to BARs 0x10…0x 24 respectively. A BIR value of 3 indicates that
the table is mapped in BAR 3 (address 0x1C).
When BARCTRL.BAR32 equals 0b (64 bit MMIO mapping) the table BIR equals 0x4. When
BARCTRL.BAR32 equals 1b (32 bit MMIO mapping) the table BIR equals 0x3.
Bit(s) R/W Initial Value Description
30:0 R/W
1
1. In the event that the CSR_conf_en bit in the PCIe Init Configuration 2 Flash word is cleared, accesses to the IOADDR register via
configuration address space is ignored and has no effect on the register and the CSRs referenced by the IOADDR register.
0x0
Internal Register or Internal Memory location Address.
0x00000-0x1FFFF – Internal Registers and Memories
0x20000-0x7FFFFFFF – Undefined
31 R/W 0b
Configuration IO Access Enable.
0b - CSR configuration read or write disabled.
1b - CSR Configuration read or write enabled
When bit is set accesses to the IODATA register actually generate transactions to the
device. Otherwise, accesses to the IODATA register are don't-cares (write are discarded
silently, reads return arbitrary results).