Data Sheet

Ethernet Controller I210 —Interconnects
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3.3.3.1 Memory Mapped Host Interface
The Flash device can be mapped into memory and/or I/O address space of the PF through the use of
Base Address Registers (BARs).
Clearing the FLBAR_Size and CSR_Size fields in PCIe Control 2 Flash word (Word 0x28) to 0b, disables
Flash mapping to PCI space via the Flash Base Address register.
Setting the LAN Boot Disable bit in the Initialization Control 3 Flash word, disables Flash mapping to the
PCI space via the Expansion ROM Base Address register
Using the legacy Flash transactions, the Flash is read from, or written to (under Flash security rules), by
The I210 each time the host CPU performs a read or a write operation to a memory location that is
within the Flash address mapping or upon boot via accesses in the space indicated by the Expansion
ROM Base Address register. Accesses to the Flash are based on a direct decode of CPU accesses to a
memory window defined in either:
• Memory CSR + Flash Base Address Register (PCIe Control Register at offset 0x10). Refer to
Section 9.3.11. Memory BAR accesses are mapped to the Flash, starting from word address 0x0,
and up to the exposed BAR size - never beyond it.
• The Expansion ROM Base Address Register (PCIe Control Register at offset 0x30). Refer to
Section 9.3.15. Expansion-ROM BAR accesses are mapped to the Flash, starting from the fixed
word address 0x1000. For example, just after the first 8 KB used for the shadow RAM banks.
a. For BAR_SIZE = 0.5 MB, read accesses to the last 8 KB of the Expansion-ROM BAR returns
unpredictable data. Refer to Figure 3-4.
b. For BAR_SIZE >= 1 MB, read accesses beyond (1 MB - 8 KB) of the Expansion-ROM BAR returns
unpredictable data. Refer to Figure 3-5.
For accesses through any of the two BARs, the following occurs:
• If the Flash part is larger than the exposed BAR size (for saving operating system address space),
accesses to the upper Flash addresses are not possible through the BAR.
• If the Flash part is smaller than the exposed BAR size (further to a wrong Flash setting or because
of the 128 KB added for CSRs), accesses are (naturally) wrapped around when attempting to
access upper addresses.
The I210 is responsible to map accesses via the Expansion ROM BAR to the physical Flash. The offset in
the Flash of the Expansion ROM module is fixed and starts at word address 0x001000.
— If there is no valid Flash Validity field in the two first 4 KB sectors, then Expansion ROM BAR is
disabled.
— When present, the Expansion-ROM module must be mapped starting from word address
0x1000. For example, just after the first 8 KB of the Flash.
— When no Expansion-ROM module is present, the Flash area starting from word address 0x1000
can be used for other modules mapped outside of the shadow RAM (such as the firmware
image).