Data Sheet

PCIe Programming Interface—Ethernet Controller I210
601
9.4.3.1 Capability ID (0x70; RO)
This field equals 0x11 indicating the linked list item as being the MSI-X registers.
9.4.3.2 Next Pointer (0x71; RO)
This field provides an offset to the next capability item in the capability list. Its value of 0xA0 points to
the PCIe capability.
9.4.3.3 Message Control (0x72; R/W)
The register fields are described in the following table. There is a dedicated register per PCI function to
separately
configure their MSI-X functionality.
Table 9-8. MSI-X Capability Structure
Byte Offset Byte 3 Byte 2 Byte 1 Byte 0
0x70 Message Control (0x00090) Next Pointer (0xA0) Capability ID (0x11)
0x74 Table Offset
0x78 PBA offset
Bits Default R/W Description
10:0 0x004
1
1. Default value is read from the Flash.
RO
TS - Table Size
System software reads this field to determine the MSI-X Table Size N, which is encoded as N-
1. For example, a returned value of 0x00F indicates a table size of 16.
The I210 supports 5 MSI-X vectors.
This field is loaded from the MSI-X Configuration (Offset 0x16) Flash word.
13:11 000b RO
Reserved
Always return 000b on read. Write operation has no effect.
14 0b R/W
FM - Function Mask
If set to 1b, all of the vectors associated with the function are masked, regardless of their per-
vector Mask bit states.
If set to 0b, each vector’s Mask bit determines whether the vector is masked or not.
Setting or clearing the MSI-X Function Mask bit has no effect on the state of the per-vector
Mask bits.
15 0b R/W
En - MSI-X Enable
If set to 1b and the MSI Enable bit in the MSI Message Control (MMC) register is 0b, the
function is permitted to use MSI-X to request service and is prohibited from using its INTx#
pin.
System configuration software sets this bit to enable MSI-X. A software device driver is
prohibited from writing this bit to mask a function’s service request.
If set to 0b, the function is prohibited from using MSI-X to request service.