Data Sheet

PCIe Programming Interface—Ethernet Controller I210
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9.4.2.4 Message Address Low (0x54; R/W)
Written by the system to indicate the lower 32 bits of the address to use for the MSI memory write
transaction. The lower two bits always return 0b regardless of the write operation.
9.4.2.5 Message Address High (0x58; R/W)
Written by the system to indicate the upper 32-bits of the address to use for the MSI memory write
transaction.
9.4.2.6 Message Data (0x5C; R/W)
Written by the system to indicate the lower 16 bits of the data written in the MSI memory write Dword
transaction. The upper 16 bits of the transaction are written as 0b.
9.4.2.7 Mask bits (0x60; R/W)
The Mask Bits and Pending Bits registers enable software to disable or defer message sending on a per-
vector basis. As the I210 supports only one message, only bit 0 of these register is implemented.
9.4.2.8 Pending Bits (0x64; R/W)
9.4.3 MSI-X Configuration
More than one MSI-X capability structure is prohibited, but a function is permitted to have both an MSI
and an MSI-X capability structure.
71bRO
64-bit capable
A value of 1b indicates that the I210 is capable of generating 64-bit message addresses.
81b
1
RO
MSI per-vector masking.
A value of 1b indicates that the I210 is capable of per-vector masking.
This field is loaded from the MSI-X Configuration (Offset 0x16) Flash word.
15:9 0b RO
Reserved
Write 0 ignore on read.
1. Default value is read from the Flash.
Bits Default R/W Description
00bR/W
MSI Vector 0 Mask
If set, the I210 is prohibited from sending MSI messages.
31:1 000b RO Reserved
Bits Default R/W Description
0 0b RO If set, the I210 has a pending MSI message.
31:1 000b RO Reserved
Bits Default R/W Description