Data Sheet

Ethernet Controller I210 —PCIe Programming Interface
598
For other Data_Select values, the Data register output is reserved (0x0).
9.4.2 MSI Configuration
This structure is required for PCIe devices.
9.4.2.1 Capability ID (0x50; RO)
This field equals 0x05 indicating the linked list item as being the MSI registers.
9.4.2.2 Next Pointer (0x51; RO)
This field provides an offset to the next capability item in the capability list. Its value of 0x70 points to
the MSI-X capability structure.
9.4.2.3 Message Control (0x52; R/W)
The register fields are described in the following table. There is a dedicated register per PCI function to
separately enable their MSI.
Function
D0 (Consume/
Dissipate)
D3 (Consume/
Dissipate)
Common
PMCSR.Data Select 0x0 / 0x4 0x3 / 0x7 0x8
Function 0 Flash addr 0x22 Flash addr 0x22 Flash addr 0x22
Byte Offset Byte 3 Byte 2 Byte 1 Byte 0
0x50 Message Control (0x0180) Next Pointer (0x70) Capability ID (0x05)
0x54 Message Address
0x58 Message Upper Address
0x5C Reserved Message Data
0x60 Mask bits
0x64 Pending bits
Bits Default R/W Description
00bR/W
MSI Enable
If set to 1b, equals MSI. In this case, the I210 generates an MSI for interrupt assertion instead
of INTx signaling.
3:1 000b RO
Multiple Message Capable
The I210 indicates a single requested message.
6:4 000b RO
Multiple Message Enable
The I210 returns 000b to indicate that it supports a single message.