Data Sheet

PCIe Programming Interface—Ethernet Controller I210
597
9.4.1.5 Bridge Support Extensions - PMCSR_BSE (0x46; RO)
This register is not implemented in the I210. Values are set to 0x00.
9.4.1.6 Data Register (0x47; RO)
This optional register is used to report power consumption and heat dissipation. Reported register is
controlled by the Data_Select field in the PMCSR and the power scale is reported in the Data_Scale field
in the PMCSR. The data of this field is loaded from the Flash if power management is enabled in the
Flash or with a default value of 0x00. The values for the I210 are read from Flash word 0x22.
Bits Default R/W Description
15
0b
(at power
up)
R/W1CS
PME_Status
This bit is set to 1b when the function detects a wake-up event independent of the state of the
PME_En bit. Writing a 1b clears this bit.
14:13 01b RO
Data_Scale
This field indicates the scaling factor to be used when interpreting the value of the Data
register.
This field equals 01b (indicating 0.1 watt units) if power management is enabled in the Power
Management (PM Ena) bit in Initialization Control Word 1 (word 0x0A) Flash word and the
Data_Select field is set to 0, 3, 4, 7, (or 8). Otherwise, this field equals 00b.
12:9 0000b R/W
Data_Select
This four-bit field is used to select which data is to be reported through the Data register and
Data_Scale field. These bits are writable only when power management is enabled by setting
the Power Management (PM Ena) bit in Initialization Control Word 1 (word 0x0A) Flash word.
8
0b
(at power
up)
R/WS
PME_En
If power management is enabled in the Flash, writing a 1b to this register enables wake up.
If power management is disabled in the Flash, writing a 1b to this bit has no effect and does
not set the bit to 1b.
7:4 000000b RO Reserved
31b
1
1. Loaded from Flash (See Section 6.2.17).
RO
No_Soft_Reset
No_Soft_Reset - When set (“1”), this bit indicates that when the I210 transitions from D3hot to
D0 because of modifying Power State bits in the PMCSR register, no internal reset is issued and
Configuration Context is preserved. Upon transition from the D3hot to the D0 Initialized state,
no additional operating system intervention is required to preserve Configuration Context
beyond writing the Power State bits.
When clear (“0”), the I210 performs an internal reset upon transitioning from D3hot to D0 via
software control of the Power State bits in the PMCSR register. Configuration Context is lost
when performing the soft reset. Upon transition from the D3hot to the D0 state, full re
initialization sequence is needed to return the device to D0 Initialized.
Regardless of this bit, devices that transition from D3hot to D0 by a system or bus segment
reset returns to the device state D0 Uninitialized with only PME context preserved if PME is
supported and enabled.
2 0b RO Reserved for PCIe.
1:0 00b R/W
Power State
This field is used to set and report the power state of a function as follows:
00b = D0
01b = D1 (cycle ignored if written with this value)
10b = D2 (cycle ignored if written with this value)
11b = D3 (cycle ignored if power management is not enabled in the Flash)