Data Sheet
Ethernet Controller I210 —PCIe Programming Interface
596
9.4.1.1 Capability ID (0x40; RO)
This field equals 0x01 indicating the linked list item as being the PCI Power Management registers.
9.4.1.2 Next Pointer (0x41; RO)
This field provides an offset to the next capability item in the capability list. In LAN function, a value of
0x50 points to the MSI capability.
9.4.1.3 Power Management Capabilities - PMC (0x42; RO)
This field describes the I210’s functionality at the power management states as described in the
following table. Note that each device function has its own register.
9.4.1.4 Power Management Control / Status Register - PMCSR (0x44; R/W)
This register is used to control and monitor power management events in the I210. Note that each
device function has its own PMCSR register.
Bits Default R/W Description
15:11
01001b
See value in
description
column
RO
PME_Support - This 5-bit field indicates the power states in which the function might assert
PME#. A value of 0b for any bit indicates that the function is not capable of asserting the
PME# signal while in that power state.
bit(11) X XXX1b - PME# can be asserted from D0
bit(12) X XX1Xb - PME# can be asserted from D1
bit(13) X X1XXb - PME# can be asserted from D2
bit(14) X 1XXXb - PME# can be asserted from D3hot
bit(15) 1 XXXXb - PME# can be asserted from D3cold
Value of bit 15 is a function of Aux Pwr availability and Power Management (PM Ena) bit in
Initialization Control Word 1 (word 0x0A) Flash word.
Conditionaaaaaaaaaaa Functionalityaaaaaaaaaaaaa aValue
PM Dis in Flash No PME at all states 00000b
PM Ena & NoAux Pwr PME at D0 and D3hot aaaaaaaaa 01001b
PM Ena & Aux Pwr PME at D0, D3hot and D3coldaa 11001b
Note: Aux Pwr is considered available if AUX_PWR pin is connected to 3.3V and
D3COLD_WAKEUP_ADVEN Flash bit is set to 1b.
10 0b RO
D2_Support
The I210 does not support D2 state.
90b RO
D1_Support
The I210 does not support D1 state.
8:6 000b RO AUX Current – Required current defined in the Data Register.
51b RO
DSI
The I210 requires its device driver to be executed following transition to the D0 uninitialized
state.
4 0b RO Reserved
3 0b RO
PME_Clock
Disabled. Hardwired to 0b.
2:0 011b RO
Version
The I210 complies with the PCI PM specification, revision 1.2.