Data Sheet

PCIe Programming Interface—Ethernet Controller I210
593
9.3.11.1 32-bit LAN BARs Mode Mapping
This mapping is selected when bit 10 in the Functions Control Flash word is equal to 1b.
9.3.11.2 64-bit LAN BARs Mode Mapping
This mapping is selected when bit 10 in the Functions Control Flash word is equal to 0b.
9.3.11.3 Base Address Register Fields
All base address registers have the following fields.
Table 9-4. Base Address Setting in 32bit BARs Mode (BARCTRL.BAR32 = 1b)
BAR Addr 31 - - - - - - - - - - - - - - - - - - - - - - - - - - -5 4321 0
0 0x10 Memory CSR + FLASH BAR (R/W - 31:17; RO - 16:4 (0x0)) 0/1 0 0 0
1 0x14 Reserved (read as all 0b’s)
2 0x18 IO BAR (R/W - 31:5) 0 0 0 0 1
3 0x1C MSI-X BAR (R/W - 31:14; RO - 13:4 (0x0)) 0/1 0 0 0
4 0x20 Reserved (read as all 0b’s)
5 0x24 Reserved (read as all 0b’s)
Table 9-5. Base Address Setting in 64bit BARs Mode (BARCTRL.BAR32 = 0b)
BAR Addr 31 - - - - - - - - - - - - - - - - - - - - - - - - - - -5 4321 0
0 0x10 Memory CSR + FLASH BAR Low (RW - 31:17;RO - 16:4 (0x0)) 0/1 1 0 0
1 0x14 Memory CSR + FLASH BAR High (RW)
20x18IO BAR (R/W - 31:5) 00001
3 0x1C Reserved (RO - 0)
4 0x20 MSI-X BAR Low (RW - 31:14; RO - 13:4 (0x0)) 0/1 1 0 0
50x24MSI-X BAR High (RW)
Table 9-6. Base Address Registers' Fields
Field Bits R/W Description
Mem / IO Space
Indication
0RO
0b = Indicates memory space.
1b = Indicates I/O.
Memory Type 2:1 RO
00b = 32-bit BAR (BAR32 in the Flash equals 1b)
10b = 64-bit BAR (BAR32 in the Flash equals 0b)
Prefetch Memory 3 RO
0b = Non-prefetchable space.
1b = Prefetchable space (device default).
This bit is loaded from the PREFBAR bit in the Flash. This bit should be set only on systems
that do not generate prefetchable cycles.