Data Sheet

Ethernet Controller I210 —PCIe Programming Interface
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9.3.5 Revision (0x8; RO)
The default revision ID for the I210 A1 stepping is 0x01 and 0x03 for A2 stepping. The value of the rev
ID is a logic XOR between the default value and the value in Flash word 0x1E.
9.3.6 Class Code (0x9; RO)
The class code is a RO hard coded value that identifies the I210’s functionality.
• 0x020000/0x010000 - Ethernet/SCSI Adapter
1
9.3.7 Cache Line Size (0xC; R/W)
This field is implemented by PCIe devices as a read-write field for legacy compatibility purposes but has
no impact on any PCIe device functionality. Field is loaded from the PCIe Init Configuration 3 (Word
0x1A) Flash word and defines cache line size in Dwords. In systems, the value is 0x10.
9.3.8 Latency Timer (0xD; RO)
Not used. Hardwired to zero.
9.3.9 Header Type (0xE; RO)
This indicates if a device is single function or multifunction. If a single LAN function is the only active
one then this field has a value of 0x00 to indicate a single function device.
9.3.10 BIST (0xF; RO)
BIST is not supported in the I210.
9.3.11 Base Address Registers (0x10...0x27; R/W)
The Base Address registers (BARs) are used to map the I210 register space. The I210 has a memory
BAR, IO BAR and MSI-X BAR described in Table 9-3 below.
1. Selected according to bit 11 in Device Rev ID Flash word.
Table 9-3. Base Address Registers Description -
Mapping Windows Mapping Description
Memory BAR
The internal registers memories and external Flash device are accessed as direct memory mapped offsets
from the Base Address register. Software can access a Dword or 64 bits.
The Flash space in this BAR is enabled by the FLBARSize and CSRSize fields in the BARCTRL register.
Address 0 in the Flash device is mapped to address 128K in the Memory BAR. When the usable Flash size
+ CSR space is smaller than the memory BAR, then accessing addresses above the top of the Flash
wraps back to the beginning of the Flash.
IO BAR
All internal registers and memories can be accessed using I/O operations. There are two 4-byte registers
in the IO mapping window: Addr Reg and Data Reg accessible as Dword entities. I/O BAR support
depends on the IO_Sup bit in the Flash “PCIe Init Configuration 2” word.
MSI-X BAR
The MSI-X vectors and Pending bit array (PBA) structures are accessed as direct memory mapped offsets
from the MSI-X BAR. Software can access Dword entities.