Data Sheet

PCIe Programming Interface—Ethernet Controller I210
591
9.3.3 Command Register (0x4; R/W)
This is a read/write register.
9.3.4 Status Register (0x6; RO)
Bit(s) R/W Initial Value Description
0 R/W
1
1. If IO_Sup bit in PCIe Init Configuration 2 Flash Word (0x19) is 0, I/O Access Enable bit is RO with a value of 0.
0b I/O Access Enable
1 R/W 0b Memory Access Enable
2 R/W 0b Bus Master Enable (BME)
3 RO 0b
Special Cycle Monitoring
Hardwired to 0b.
4 RO 0b
MWI Enable
Hardwired to 0b.
5 RO 0b
Palette Snoop Enable
Hardwired to 0b.
6 RW 0b Parity Error Response
7 RO 0b
Wait Cycle Enable
Hardwired to 0b.
8 RW 0b SERR# Enable
9 RO 0b Fast Back-to-Back Enable
10 RW 0b Interrupt Disable
2
2. The Interrupt Disable register bit is a read-write bit that controls the ability of a PCIe device to generate a legacy interrupt message.
When set, devices are prevented from generating legacy interrupt messages.
15:11 RO 0x0 Reserved
Bits R/W Initial Value Description
2:0 000b Reserved
3 RO 0b Interrupt Status
1
1. The Interrupt Status field is a RO field that indicates that an interrupt message is pending internally to the device.
4 RO 1b
New Capabilities
Indicates that a device implements extended capabilities. The I210 sets this bit, and
implements a capabilities list, to indicate that it supports PCI power management, Message
Signaled Interrupts (MSI), Enhanced Message Signaled Interrupts (MSI-X), Vital Product
Data (VPD), and the PCIe extensions.
5 0b
66 MHz Capable
Hardwired to 0b.
6 0b Reserved
7 0b
Fast Back-to-Back Capable
Hardwired to 0b.
8 R/W1C 0b Data Parity Reported
10:9 00b
DEVSEL Timing
Hardwired to 0b.
11 R/W1C 0b Signaled Target Abort
12 R/W1C 0b Received Target Abort
13 R/W1C 0b Received Master Abort
14 R/W1C 0b Signaled System Error
15 R/W1C 0b Detected Parity Error