Data Sheet

Ethernet Controller I210 —PCIe Programming Interface
588
The PCI configuration registers map is listed in Table 9-2. Refer to a detailed description for registers
loaded from the Flash at initialization time. Note that initialization values of the configuration registers
are marked in parenthesis.
9.2.2 PCIe Configuration Space Summary
RWS
Read-write register: Register bits are read-write and can be either set or reset by software to the desired
state. Bits are not cleared by reset and can only be reset with the PWRGOOD signal. Devices that consume
AUX power are not allowed to reset sticky bits when AUX power consumption (either via AUX power or PME
enable) is enabled.
R/W1CS
Read-only status, write-1-to-clear status register: Register bits indicate status when read, a set bit indicating
a status event can be cleared by writing a 1b. Writing a 0b to R/W1C bits has no effect. Bits are not cleared
by reset and can only be reset with the PWRGOOD signal. Devices that consume AUX power are not allowed
to reset sticky bits when AUX power consumption (either via AUX power or PME enable) is enabled.
HwInit
Hardware initialized: Register bits are initialized by firmware or hardware mechanisms such as pin strapping
or serial Flash. Bits are read-only after initialization and can only be reset (for write-once by firmware) with
PWRGOOD signal.
RsvdP
Reserved and preserved: Reserved for future R/W implementations; software must preserve value read for
writes to bits.
RsvdZ Reserved and zero: Reserved for future R/W1C implementations; software must use 0b for writes to bits.
Table 9-2. PCIe Configuration Registers Map -
Section
Byte
Offset
Byte 3 Byte 2 Byte 1 Byte 0
Mandatory PCI
register
0x0 Device ID Vendor ID
0x4 Status Register Control Register
0x8 Class Code (0x020000/0x010000) Revision ID
0xC BIST (0x00)
Header Type (0x0/
0x80)
Latency Timer Cache Line Size (0x10)
0x10 Base Address Register 0
0x14 Base Address Register 1
0x18 Base Address Register 2
0x1C Base Address Register 3
0x20 Base Address Register 4
0x24 Base Address Register 5
0x28 CardBus CIS pointer (0x0000)
0x2C Subsystem Device ID Subsystem Vendor ID
0x30 Expansion ROM Base Address
0x34 Reserved Cap Ptr (0x40)
0x38 Reserved
0x3C Max Latency (0x00) Min Grant (0x00)
Interrupt Pin
(0x01...0x04)
Interrupt Line (0x00)
Power
management
capability
0x40 Power Management Capabilities Next Pointer (0x50) Capability ID (0x01)
0x44 Data
Bridge Support
Extensions
Power Management Control & Status
Table 9-1. Configuration Registers (Continued)