Data Sheet

Ethernet Controller I210 — Programming Interface
584
8.27.5.7 Polarity Control - Page 26, Register 27
8.27.5.8 SerDes TX FIFO Control and Status - Page 26, Register 28
Bits Field Mode HW Rst SW Rst Description
15
Invert rxp/n
Polarity
R/W Retain
The latest event that occurs between the register write and pin
control determines the polarity.
0b = Normal.
1b = Invert.
14
Invert txp/n
Polarity
R/W Retain
The latest event that occurs between the register write and pin
control determines the polarity.
0b = Normal.
1b = Invert.
13:2 Reserved R/W 0x0 Retain Reserved for future use.
1:0
SQ Control
Selection
R/W 0x Retain
Squelch detector threshold control.
00b = 30 mV.
01b = 60 mV.
10b = 90 mV.
11b = 120 mV.
Bits Field Mode HW Rst SW Rst Description
15:14
SerDes Transmit
FIFO Depth
R/W 0x0 Retain
00b = Read/write pointers are offset by two cycles.
01b = Read/write pointers are offset by three cycles.
1xb = Reserved.
13:2 Reserved R/W 0x0 Retain 0x0.
1 FIFO Full RC 0b Retain 1b = FIFO full, clear upon read.
0 FIFO Empty RC 0b Retain 1b = FIFO empty, clear upon read.