Data Sheet

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Ethernet Controller I210 —Interconnects

Figure 3.3. Flash Shadow RAM

Following a write access by software or firmware to the shadow RAM, the data should finally be updated

in the Flash as well. The I210 manageability updates the Flash from the shadow RAM when software

requests explicitly to update the Flash by setting the FLUPD bit in the EEC register. For saving Flash

updates, it is expected that software set the FLUPD bit only once it has completed the last write access

to the Flash. The I210 manageability then copies the content of the shadow RAM to the non-valid

configuration sector and makes it the valid one.

Notes: Software should be aware that programming the Flash might require a long latency due to the

Flash update sequence handled by manageability. The sector erase command by itself can

last hundreds of milliseconds. Software must poll the FLUDONE bit in the EEC register to

check whether or not the Flash programming completed.

Each time the Flash content is not valid (blank configuration sectors or wrong NVM Validity

field contents in both sector 0 and 1) EEPROM access mode is turned off. Software should

rather use one of the three flash access means described in Section 3.3.3.

3.3.2.1 Protected Areas and Words

The I210 provides a mechanism to define selected areas (two areas) in the shadow RAM that cannot be

written by the host; however, the protected areas can be read by the host. They can be write accessed

only by the manageability subsystem. The two protected areas are defined via the following registers:

1. The first protected area is a segment defined by words 0x2D and 0x2C that define the start and the

end of this read-only area. They are used to load the 1st Start Address and the 1st End Address

fields in EEBLKBASE and EEBLKEND registers, respectively.

2. The second protected area is located at the end of the 4 KB shadow RAM. Its size from the shadow

RAM’s end is defined in Flash word 0x12. It is used to load the 2nd Start Address field is

EEBLKBASE register.

For security reasons, the following Flash modules must be mapped into one of the protected areas:

• SW Reset CSR Auto Configuration Pointer (LAN Base Address + Offset 0x17) - Section 6.3

• PCIe Reset CSR Auto Configuration Pointer (LAN Base Address + Offset 0x23) - Section 6.4

• CSR Auto Configuration Power-Up Pointer (Offset 0x27) - Section 6.5

Sector 0

Sector 1

Shadow RAM

I210

Flash

EEPROM-

Mode Access

0x000FFF -

0x000000

0x000FFF

0x001000

0x001FFF

0x002000

0xFFFFFF

0x000000

0x000FFF

1:1

Physical Byte

address

Flash-Mode

Access

0xFFFFFF -

0x000000

Logical

address

Internal RAM

address

4KB