Data Sheet

Ethernet Controller I210 — Programming Interface
578
8.27.3.35 Copper Port CRC Counters - Page 6, Register 17
8.27.3.36 Checker Control - Page 6, Register 18
8.27.3.37 Misc Test - Page 6, Register 26
Bits Field Mode HW Rst SW Rst Description
15:8 Packet Count RO 0x0 Retain
0x00 = no packets received.
0xFF = 256 packets received (max count).
Bit 16_6.4 must be set to 1b in order for register to be valid.
7:0 CRC Error Count RO 0x0 Retain
0x00 = no CRC errors detected in the packets received.
0xFF = 256 CRC errors detected in the packets received (max
count).
Bit 16_6.4 must be set to 1b in order for register to be valid.
Bits Field Mode HW Rst SW Rst Description
15:5 Reserved R/W 0x000 Retain Reserved.
4
CRC Counter
Reset
R/W, SC 0x0 0x0
1b = Reset.
This bit self clears after write to 1b..
3 Enable Stub Test R 0x0 Retain
1b = Enable stub test.
0b = Normal operation.
2:0 Reserved R/W 0x0 Retain Reserved.
Bits Field Mode HW Rst SW Rst Description
15 TX_TCLK Enable R/W 0x0 0x0
The highest numbered enabled port drives the transmit clock to the
HSDACP/N pin.
1b = Enable.
0b = Disable.
14:13 Reserved R/W 0x0 Retain Reserved.
12:8 Reserved R/W 0x19 Retain Reserved.
7 Reserved R/W 0x0 Retain Reserved.
6 Reserved RO, LH 0x0 0x0 Reserved.
5 Reserved R/W 0x0 Retain Reserved.
4:0 Reserved RO xxxxx xxxxx Reserved.