Data Sheet

Interconnects—Ethernet Controller I210
57
As a physical recovery method required for manufacturing, the non-secure mode can also be entered
by setting a strapping option. Only host access to Flash and shadow RAM is guaranteed when in this
mode.
Similarly, as a means to recover from an operational error that might occur during Flash programming,
the ROM-based firmware enters the device into non-secure mode if the I210 Blank Flash Device ID field
content read from the firmware image is not 0x1531, which is used by the tools for specific the I210
SKUs.
Unless specified otherwise, secure mode is assumed throughout this document.
3.3.2 Shadow RAM
The I210 maintains the first two 4 KB sectors, Sector 0 and Sector 1, for the hardware configuration
content. At least one of these two sectors must be valid at any given time or else the I210 is set by
hardware default (iNVM). Following a Power On Reset (POR), the I210 copies the valid lower 4 KB
sector of the Flash device into an internal shadow RAM. Any further accesses of the software or
firmware to this section of the Flash are directed to the internal shadow RAM. After a software
command, modifications made to the shadow RAM content are then copied by the I210 manageability
into the other 4 KB sector of the Flash, flipping circularly the valid sector between sector 0 and 1 of
Flash.
Due to Flash security reasons, hardware does not allow any Flash accesses until the Flash is
authenticated and the blocked (protected) sections of the Flash are identified. See more on Flash
security in Section 3.3.10.
This mechanism provides the following advantages:
1. A seamless backward compatible read/write interface for software to the first 4 KB of the Flash as if
an external EEPROM device was connected. This interface is referred as EEPROM-mode access to
the Flash.
2. A way for software to protect image-update procedure from power down events by establishing a
double-image policy. It relies on having pointers to all the other Flash modules mapped in the Flash
sector which is mirrored in the internal shadow RAM.
Figure 3.3 shows the shadow RAM mapping and interface.