Data Sheet

Ethernet Controller I210 — Programming Interface
570
8.27.3.25 MAC Specific Status Register - Page 2, Register 19
8.27.3.26 Copper RX_ER Byte Capture Register - Page 2, Register 20
3
FIFO Idle Inserted
Interrupt Enable
R/W 0x0 Retain
1b = Interrupt enable.
0b = Interrupt disable.
2
FIFO Idle Deleted
Interrupt Enable
R/W 0x0 Retain
1b = Interrupt enable.
0b = Interrupt disable.
1:0 Reserved R/W 0x0 Retain 0x0.
Bits Field Mode HW Rst SW Rst Description
15:8 Reserved RO
Always
0x0
Always
0x0
Reserved.
7
Copper FIFO Over/
Underflow
RO,LH 0x0 0x0
1b = Over/underflow error.
0b = No FIFO error.
6:4 Reserved RO
Always
0x0
Always
0x0
Reserved.
3
Copper FIFO Idle
Inserted
RO,LH 0x0 0x0
1b = Idle inserted.
0b = No idle inserted.
2
Copper FIFO Idle
Deleted
RO,LH 0x0 0x0
1b = Idle deleted.
0b = Idle not deleted.
1:0 Reserved RO
Always
0x0
Always
0x0
Reserved.
Bits Field Mode HW Rst SW Rst Description
15 Capture Data Valid RO 0x0 0x0
1b = Bits 14:0 valid,
0b = Bits 14:0 invalid.
14 Reserved RO 0x0 0x0 Reserved.
13:12 Byte Number RO 0x0 0x0
00b = 4 bytes before RX_ER asserted,
01b = 3 bytes before RX_ER asserted,
10b = 2 bytes before RX_ER asserted,
11b = 1 byte before RX_ER asserted,
The byte number increments after every read when register
20_2.15 is set to 1b.
11:10 Reserved RO 0x0 0x0 Reserved.
9 RX_ER RO 0x0 0x0
RX Error.
Normally this bit is low since the capture is triggered by RX_ER
being high. However, it is possible to see an RX_ER high when the
capture is re-enabled after reading the fourth byte and there
happens to be a long sequence of RX_ER when the capture
restarts.
8 RX_DV RO 0x0 0x0 RX Data Valid.
7:0 RXD[7:0] RO 0x0 0x0 RX Data.