Data Sheet

Programming Interface — Ethernet Controller I210
569
8.27.3.23 MAC Specific Control Register 1 - Page 2, Register 16
8.27.3.24 MAC Specific Interrupt Enable Register - Page 2, Register 18
3:2 100 MB test select R/W 0x0 Retain
0xb = Normal 0peration.
10b = Select 112 ns sequence.
11b = Select 16 ns sequence.
1
10 BT polarity
force
R/W 0x0 Retain
1b = Force negative polarity for receive only.
0b = Normal operation.
0 Reserved R/W 0x0 Retain Reserved.
Bits Field Mode HW Rst SW Rst Description
15:14
Copper Transmit
FIFO Depth
R/W Retain
00b = ± 16 bits.
01b = ± 24 bits.
10b = ± 32 bits.
11b = ± 40 bits.
13:10 Reserved R/W 0x8 Update Reserved.
9 fi_125_clk control R/W Retain
1b = Stop fi_125_clk.
0b = Enable fi_125_clk.
8 fi_50_clk control R/W Retain
1b = Stop fi_50_clk.
0b = Enable fi_50_clk.
7:4 Reserved R/W 0x0 Update Reserved.
3
MAC Interface
Power Down
R/W 0x1 Update
Changes to this bit are disruptive to the normal operation.As a
result, any changes to these registers must be followed by a
software reset to take effect.
This bit determines whether the MAC interface powers down when
register 0_0.11, 16_0.2 are used to power down the device or
when the PHY enters the energy detect state.
1b = Always power up.
0b = OK to power down.
2:0 Reserved R/W 0x0 Retain
Reserved
Bits Field Mode HW Rst SW Rst Description
15:8 Reserved R/W 0x0 Retain 0x0.
7
FIFO Over/
Underflow
Interrupt Enable
R/W 0x0 Retain
1b = Interrupt enable.
0b = Interrupt disable.
6:4 Reserved R/W 0x0 Retain 0x0.