Data Sheet

Ethernet Controller I210 — Programming Interface
562
8.27.3.12 MMD Access Control Register (MMDAC) - Page 0, Register 13
8.27.3.13 MMD Access Address/Data Register (MMDAAD) - Page 0, Register 14
8.27.3.14 Extended Status Register - Page 0, Register 15
8.27.3.15 Copper Specific Control Register 1 - Page 0, Register 16
Bits Field Mode HW Rst SW Rst Description
15:14 Function R/W 0x0 0x0
00b = Address.
01b = Data, no post increment.
10b = Data, post increment on reads and writes.
11b = Data, post increment on writes only.
13:5 Reserved RO 0x000 0x000 Reserved.
4:0 DEVAD RO 0x00 0x00 Device Address.
Bits Field Mode HW Rst SW Rst Description
15:0 Address Data R/W 0x0000 0x0000
If 13.15:14 = 00b, MMD DEVAD’s address register. Otherwise,
MMD DEVAD is data register as indicated by the contents of its
address register.
Bits Field Mode HW Rst SW Rst Description
15
1000BASE-X Full-
Duplex
RO
Always
0b
Always
0b
0b = Not 1000BASE-X full-duplex capable.
14
1000BASE-X Half-
Duplex
RO
Always
0b
Always
0b
0b = Not 1000BASE-X half-duplex capable.
13
1000BASE-T Full-
Duplex
RO
Always
1b
Always
1b
1b = 1000BASE-T full-duplex capable.
12
1000BASE-T Half-
Duplex
RO
Always
1b
Always
1b
1b = 1000BASE-T half-duplex capable.
11:0 Reserved RO 0x000 0x000 Reserved.
Bits Field Mode HW Rst SW Rst Description
15 Disable Link Pulses R/W 0x0 0x0
1b = Disable link pulse.
0b = Enable link pulse.
14:12 Downshift counter R/W 0x3 Update
Changes to these bits are disruptive to the normal operation. As a
result, any changes to these registers must be followed by
software reset to take effect. 1x, 2x, ...8x is the number of times
the PHY attempts to establish GbE link before the PHY downshifts
to the next highest speed.
000b = 1x 100 = 5x.
001b = 2x 101 = 6x.
010b = 3x 110 = 7x 011 = 4x.
111b = 8x.