Data Sheet
Ethernet Controller I210 — Programming Interface
552
8.27.3.1 Copper Control Register - Page 0, Register 0
MAC Specific Control Register 1 Page 2, Register 16 section 8.27.3.23 on page 569.
MAC Specific Interrupt Enable Register Page 2, Register 18 section 8.27.3.24 on page 569.
MAC Specific Status Register Page 2, Register 19 section 8.27.3.25 on page 570.
Copper RX_ER Byte Capture Page 2, Register 20 section 8.27.3.26 on page 570.
MAC Specific Control Register 2 Page 2, Register 21 section 8.27.3.27 on page 571.
jt_led_s[3:0] Function Control Register Page 3, Register 16 section 8.27.3.28 on page 572.
jt_led_s[3:0] Polarity Control Register Page 3, Register 17 section 8.27.3.29 on page 574.
LED Timer Control Register Page 3, Register 18 section 8.27.3.30 on page 574.
jt_led_s[5:4] Function Control and Polarity Register Page 3, Register 19 section 8.27.3.31 on page 575.
1000BASE-T Pair Skew Register Page 5, Register 20 section 8.27.3.32 on page 576.
1000BASE-T Pair Swap and Polarity Page 5, Register 21 section 8.27.3.33 on page 577.
Copper Port Packet Generation Page 6, Register 16 section 8.27.3.34 on page 577.
Copper Port CRC Counters Page 6, Register 17 section 8.27.3.35 on page 578.
Checker Control Page 6, Register 18 section 8.27.3.36 on page 578.
Misc Test Page 6, Register 26 section 8.27.3.37 on page 578.
Bits Field Mode HW Rst SW Rst Description
15 Copper Reset R/W, SC 0x0 SC
Copper Software Reset.
Affects pages 0, 2, 3, 5, and 7. Writing a 1b to this bit causes the
PHY state machines to be reset. When the reset operation
completes, this bit is cleared to 0b automatically. The reset occurs
immediately.
1b = PHY reset.
0b = Normal operation.
14 Loopback R/W 0x0 0x0
When loopback is activated, the transmitter data presented on
TXD is looped back to RXD internally. Link is broken when
loopback is enabled. Loopback speed is determined by Registers
21_2.2:0.
1b = Enable loopback.
0b = Disable loopback.
13
Speed Select
(LSB)
R/W 0x0 Update
Changes to this bit are disruptive to the normal operation. As a
result, any changes to these registers must be followed by a
software reset to take effect.
A write to this register bit does not take effect until any one of the
following also occurs:
• Software reset is asserted (register 0_0.15).
• Restart auto-negotiation is asserted (register 0_0.9).
• Power down (register 0_0.11, 16_0.2) transitions from power
down to normal operation.
Bits 6and 13:
11b = Reserved.
10b = 1000 Mb/s.
01b = 100 Mb/s.
00b = 10 Mb/s.