Data Sheet

Programming Interface — Ethernet Controller I210
551
8.27.3 Internal PHY Software Interface (PHYREG)
1. Base registers (page 0, registers 0 through 10 and 15) are defined in accordance with the
Reconciliation Sub layer and Media Independent Interface and Physical Layer Link Signaling for 10/
100/ 1000 Mb/s Auto-Negotiation sections of the IEEE 802.3 specification.
2. Additional registers are defined in accordance with the IEEE 802.3 specification for adding unique
chip functions.
3. Registers in the following table are accessed using the internal MDIO interface via the MDIC register
(Refer to Section 8.2.4).
Disable 1000 6 0b
When set, disables 1000 Mb/s in all power modes.
This bit is loaded from the Giga Disable bit in the Software Defined Pins
Control Flash word on reset.
SPD_B2B_EN 7 1b SPD Back-to-Back Enable.
rst_compl (RO, LH) 8 0b Indicates PHY internal reset cleared.
Disable 100 in non-D0a 9 0b
Disables 100 Mb/s and 1000 Mb/s operation in non-D0a states.
This bit is loaded from the Disable 100 in non-D0a bit in the Software
Defined Pins Control Flash word on reset.
Reserved 31:10 0x0
Reserved.
Write 0x0, ignore on read.
Register Name Register Address Section and Page
Copper Control Register Page 0, Register 0 section 8.27.3.1 on page 552.
Copper Status Register Page 0, Register 1 section 8.27.3.2 on page 554.
PHY Identifier 1 Page 0, Register 2 section 8.27.3.3 on page 555.
PHY Identifier 2 Page 0, Register 3 section 8.27.3.4 on page 555.
Copper Auto-Negotiation Advertisement Register Page 0, Register 4 section 8.27.3.5 on page 555.
Copper Link Partner Ability Register - Base Page Page 0, Register 5 section 8.27.3.6 on page 557.
Copper Auto-Negotiation Expansion Register Page 0, Register 6 section 8.27.3.7 on page 558.
Copper Next Page Transmit Register Page 0, Register 7 section 8.27.3.8 on page 559.
Copper Link Partner Next Page Register Page 0, Register 8 section 8.27.3.9 on page 559.
1000BASE-T Control Register Page 0, Register 9 section 8.27.3.10 on page 560.
1000BASE-T Status Register Page 0, Register 10 section 8.27.3.11 on page 561.
MMD Access Control Register Page 0, Register 13 section 8.27.3.12 on page 562.
MMD Access Address/Data Register Page 0, Register 14 section 8.27.3.13 on page 562.
Extended Status Register Page 0, Register 15 section 8.27.3.14 on page 562.
Copper Specific Control Register 1 Page 0, Register 16 section 8.27.3.15 on page 562.
Copper Specific Status Register 1 Page 0, Register 17 section 8.27.3.16 on page 564.
Copper Specific Interrupt Enable Register Page 0, Register 18 section 8.27.3.17 on page 565.
Copper Interrupt Status Register Page 0, Register 19 section 8.27.3.18 on page 566.
Copper Specific Control Register 2 Page 0, Register 20 section 8.27.3.19 on page 567.
Copper Specific Receive Error Counter Register Page 0, Register 21 section 8.27.3.20 on page 567.
Page Address Page Any, Register 22 section 8.27.3.21 on page 567.
Copper Specific Control Register 3 Page 0, Register 23 section 8.27.3.22 on page 568.
Field Bit(s) Initial Value Description