Data Sheet

Programming Interface — Ethernet Controller I210
549
8.26 Diagnostic Registers Description
8.26.1
PCIe Misc. Register - PCIEMISC (0x5BB8; RW)
Note: Reset by PCIe power good reset.
8.27 PHY Software Interface
8.27.1 Internal PHY Configuration - IPCNFG (0x0E38, RW)
The IPCNFG register controls PHY configuration.
EEE_FRC_AN 28 0b
Force EEE Auto-negotiation.
When this bit is set to 1b,it enables EEE operation in the internal MAC logic even
if the link partner does not support EEE. Should be set to 1b to enable testing of
EEE operation via MAC loopback (refer to y).
EEE NEG (RO) 29 X
EEE Support Negotiated on Link.
0b = EEE operation not supported on link.
1b = EEE operation supported on link.
Note: Status reported by this bit shall be ignored when the port is operated in
half duplex mode.
RX LPI Status (RO) 30 X
Rx Link in LPI State.
0b = Rx in active state.
1b = Rx in LPI state.
TX LPI Status (RO) 31 X
Tx Link in LPI State.
0b = Tx in active state.
1b = Tx in LPI state.
1. Loaded from Flash.
Field Bit(s)
Initial
Value
Description
Reserved 8:0 0x8A
Reserved
Ignore on read, write 0x8A.
DMA Idle Indication 9 0b
1
1. Value loaded from Flash.
Pulses shorter than the filter width are ignored.
Indication For DMA Idle
This bit indicates when DMA is considered idle (either when the DMA is idle or when PCIe
Link is idle).
0b = DMA is considered idle when there is no Rx or Tx.
1b = DMA is considered idle when there is no Rx or Tx AND when there are no TLPs
indicating that CPU is active detected on the PCIe link (such as the host executes CSR or
Configuration register read or write operation).
Note: The bit must be set to 1b each time programming the Flash via CSR accesses.
Reserved 31:10 0x122
Reserved
Ignore on read, write 122.
Field Bit(s) Initial Value Description