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Data Sheet

ManualsBrandsIntel ManualsComputing & OfficeIntel Intel Ethernet Server Adapter I210-T1 - Network adapter 1 Gbps LAN (10/100/1000 Mbps), PCI-Express
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Programming Interface — Ethernet Controller I210
547
8.25.11 Latency Tolerance Reporting (LTR) Control - LTRC (0x01A0; R/
W)
Field Bit(s) Initial Value Description
Reserved 0 0b
Reserved.
Write 0b, ignore on read.
LTR_MIN 1 0b
LTR Send Minimum Values.
When set to 1b, the I210 sends a PCIe LTR message with the LTR snoop value, LTR
no-snoop value and LTR requirement bits as defined in the LTRMINV register.
Notes:
1. To resend a LTR message with the minimum value defined in the LTRMINV
register, this bit should be cleared and set again.
2. LTR_MIN and LTR_MAX bits are exclusive.
3. A new PCIe LTR message is sent only if the last PCIe LTR message sent had a
latency tolerance value different then the value specified in the LTRMINV register.
LTR_MAX 2 0b
LTR Send Maximum Values.
When set to 1b, the I210 sends a PCIe LTR message with the LTR snoop value, LTR
no-snoop value and LTR requirement bits as defined in the LTRMAXV register.
Notes:
1. To resend a LTR message with the maximum value defined in the LTRMAXV
register, this bit should be cleared and set again.
2. LTR_MIN and LTR_MAX bits are exclusive.
3. A new PCIe LTR message is sent only if the last PCIe LTR message sent had a
latency tolerance value different then the value specified in the LTRMAXV
register.
PDLS_EN 3 1b
Port Disable LTR Send Enable.
0b = Do not issue a PCIe LTR message with requirement bits cleared on port disable
(Rx and Tx disabled).
1b = Issue a PCIe LTR message with requirement bits cleared on port disable (Rx and
Tx disabled).
LNKDLS_EN 4 1b
Link Disconnect LTR Send Enable.
0b = Do not issue a PCIe LTR message with requirement bits cleared on link
disconnect.
1b = Issue a PCIe LTR message with requirement bits cleared on link disconnect.
EEEMS_EN 5 0b
EEE LPI LTR Max Send Enable.
When this bit is set and link is in a Rx EEE LPI (Low Power Idle) state, the I210 sends
a PCIe LTR message with the LTR snoop value, LTR no-snoop value and LTR
requirement bits as defined in the LTRMAXV register.
0b = Do not issue a PCIe LTR messages with the LTRMAXV value as a result of Rx link
entering EEE LPI state.
1b=Issue PCIe LTR messages with a LTRMAXV value as a result of Rx link entering EEE
LPI state.
Note: This bit is reset to 0b by hardware following link disconnect to enable
software to re-negotiate Tw_system time and update the LTRMAXV value.
Reserved 31:6 0x0
Reserved.
Write 0x0, ignore on read.