Data Sheet

Programming Interface — Ethernet Controller I210
541
8.24.11 LAN Port Parity Error Status Register - LANPERRSTS (0x5F58; R/
W1C
)
8.25 Power Management Register Description
The following registers are used to control various power saving features.
8.25.1 DMA Coalescing Control Register - DMACR (0x2508; R/W)
Field Bit(s)
Initial
Value
Description
Reserved 8:0 0x0
Reserved.
Write 0x0, ignore on read.
retx_buf 9 0b
retx_buf Parity Error Indication.
When set to 1b, indicates detection of parity error in the RETX buffer (re-transmit buffer)
RAM if LANPERRCTL.retx_buf_en is set.
When set, disables packet transmission. To recover from this condition, the software
device driver should issue a software reset by asserting CTRL.RST and re-initializing the
port.
Note: PEIND.lanport_parity_fatal_ind and ICR.FER interrupts are asserted if bits are
not masked.
Reserved 31:10 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
DMACWT 13:0 0x20
DMA Coalescing Watchdog Timer.
When in DMA coalescing, the value in the DMACR.DMACWT counter sets the upper
limit in 32.768 µs units between receive packet arrival as well as the request to
transmit or issue an interrupt cause to move out of DMA coalescing.
Note: If the value is 0x0, a condition to move out of DMA coalescing is a result of
the watchdog timer expiration being disabled.
Reserved 14 0b Reserved.
DC_BMC2OSW_EN 15 1b
DMA Coalescing MC-to-OS Watchdog Enable.
When set to 1b, MC-to-OS traffic activate the DMA coalescing watchdog timer
(DMACR.DMACWT).
Note: If the DMA coalescing watchdog timer is disabled and this bit is set 1b, any
MC-to-OS traffic causes a move out of the DMA coalescing state.
DMACTHR 23:16 0x0
DMA Coalescing Receive Threshold.
This value defines the DMA coalescing receive threshold in 1 KB units. When the
amount of data in the internal receive buffer exceeds the DMACTHR value, DMA
coalescing is stopped and PCIe moves to the L0 state.
Notes:
1. This value should be lower than the FCRTC.RTH_Coal threshold value to avoid
generating needless flow control packets when in DMA coalescing operating
mode and flow control is enabled.
2. The receive threshold size should be smaller than the internal receive buffer area
reported in the RXPBSIZE.RXPbsize field.
3. If the value is 0x0, condition to move out of DMA coalescing as a result of
passing DMA coalescing receive threshold is disabled.
4. The value programmed should be greater than maximum packet size.
Reserved 24 0b
Reserved.
Write 0b, ignore on read.