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Data Sheet

ManualsBrandsIntel ManualsComputing & OfficeIntel Intel Ethernet Server Adapter I210-T1 - Network adapter 1 Gbps LAN (10/100/1000 Mbps), PCI-Express
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Programming Interface — Ethernet Controller I210
539
8.24.6 PCIe ECC Control Register - PCIEECCCTL (0x5BA4; RW)
Field Bit(s)
Initial
Value
Description
Reserved 2:0 0x0
Reserved.
Write 0x0, ignore on read.
PAR ERR RX CDQ 0 3 0b
Rx CDQ 0 Parity Error.
Indicates detection of parity error in RAM if PCIEERRCTL.ERR EN RX CDQ 0 is set.
When set, stops all PCIe and DMA Rx and Tx activity from the function. To recover from
this condition, the software device driver should issue a software reset by asserting
CTRL.RST and re-initializing the port (refer to Section 7.6.1.1).
Note: PEIND.pcie_parity_fatal_ind and ICR.FER interrupts are asserted if bits are not
masked.
PAR ERR RX CDQ 1 4 0b
Rx CDQ 1 Parity Error.
Indicates detection of parity error in RAM if PCIEERRCTL.ERR EN RX CDQ 1 is set.
When set, stops all PCIe and DMA Rx and Tx activity from the function. To recover from
this condition, the software device driver should issue a software reset by asserting
CTRL.RST and re-initializing the port (refer to Section 7.6.1.1).
Note: PEIND.pcie_parity_fatal_ind and ICR.FER interrupts are asserted if bits are not
masked.
PAR ERR RX CDQ 2 5 0b
RX CDQ 2 Parity Error.
Indicates detection of parity error in RAM if PCIEERRCTL.ERR EN RX CDQ 2 is set.
When set, stops all PCIe and DMA Rx and Tx activity from the function. To recover from
this condition, the software device driver should issue a software reset by asserting
CTRL.RST and re-initializing the port (refer to Section 7.6.1.1).
Note: PEIND.pcie_parity_fatal_ind and ICR.FER interrupts are asserted if bits are not
masked.
PAR ERR RX CDQ 3 6 0b
RX CDQ 3 Parity Error.
Indicates detection of parity error in RAM if PCIEERRCTL.ERR EN RX CDQ 3 is set.
When set, stops all PCIe and DMA Rx and Tx activity from the function. To recover from
this condition, the software device driver should issue a software reset by asserting
CTRL.RST and re-initializing the port (refer to Section 7.6.1.1).
Note: PEIND.pcie_parity_fatal_ind and ICR.FER interrupts are asserted if bits are not
masked.
Reserved 31:7 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s)
Initial
Value
Description
Reserved 11:0 0x511 Reserved.
ERR EN TX WR DATA 12 1b Tx Write Request Data ECC Check Enable.
Reserved 13 0b Reserved.
ERR EN RETRY BUF 14 1b Tx Retry Buffer ECC Check Enable.
Reserved 31:15 0x0
Reserved.
Write 0x0, Ignore on read.