Data Sheet

Ethernet Controller I210 — Programming Interface
538
8.24.3 Packet Buffer ECC Status - PBECCSTS (0x245c; R/W)
8.24.4 PCIe Parity Control Register - PCIEERRCTL (0x5BA0; RW)
8.24.5 PCIe Parity Status Register - PCIEERRSTS (0x5BA8
; R/W1C)
Register logs uncorrectable parity errors detected in PCIe logic.
Field Bit(s) Init. Description
ecc_en 0 0x1 ECC Enable.
Reserved 1 0x0
Reserved
Write 0, ignore on read.
pb_cor_err_sta(R/
W1C)
20x0
DBU RAM correctable error indication.
Bit is clean by write 1b.
Reserved 31:3 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s)
Initial
Value
Description
GPAR_EN 0 0b
1
1. Bit loaded from Flash.
Global Parity Enable.
When cleared, parity checking of all RAMs is disabled.
Note: This bit resets only at LAN_PWR_GOOD.
Reserved 5:1 01000b
Reserved.
Write 0x0, ignore on read.
ERR EN RX CDQ 0 6 1b
RX CDQ 0 Parity Check Enable
Reserved 7 0b Reserved.
ERR EN RX CDQ 1 8 1b
RX CDQ 1 Parity Check Enable.
Reserved 9 0b Reserved.
ERR EN RX CDQ 2 10 1b
RX CDQ 2 Parity Check Enable.
Reserved 11 0b Reserved.
ERR EN RX CDQ 3 12 1b
RX CDQ 3 Parity Check Enable.
Reserved 31:13 0x0 Reserved.