Data Sheet

Ethernet Controller I210 — Programming Interface
536
8.23.3 Host Interface Buffer Base Address - HIBBA (0x8F40; RW)
Notes:
1. This register is reset by a firmware reset.
2. This resister is accessible to the host driver only if Memory Base Enable is set in HICR; otherwise,
the register is read only to the host driver.
8.23.4 Host Interface Buffer Maximum Offset - HIBMAXOFF (0x8F44;
RO)
The register holds the maximum offset in bytes in the memory buffer that the host can access from
address 0x8800 in its address space. Any access above this value is blocked by hardware.
This register is reset by a firmware reset.
8.24 Memory Error Registers Description
Main internal memories are protected by Error Correcting Code (ECC) or parity bits. The I210 contains
several registers that enable and report detection of internal memory errors. Description and usage of
these registers can be found in Section 7.6.
Field Bit(s) Initial Value Description
BA 19:0 0x17800
Host interface buffer base address in the device internal memory
space (in bytes). Base address for the CSR slave access.
The address must be 1 KB aligned (bits 9:0 are RO hardwired to
zero).
Reserved 31:20 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
MAXOFF 9:0 0x3FF
Maximum offset in the HIB for the CSR slave access.
The 2 LSBs are always set to 11b.
Reserved 31:10 0x0
Reserved.
Write 0x0, ignore on read.