Data Sheet

Programming Interface — Ethernet Controller I210
535
8.23.1.1 Host Slave Command I/F Flow
This interface is used for the external host software to access the MMS sub-system. The host software
can write a command block or read data structure directly from the DATA RAM. The host software
controls these transactions through a slave access to the control register.
The following flow describes the process of initiating a command to the MMS:
1. The software device driver takes ownership of the SW_FW_SYNC.SW_MNG_SM bit according to the
flow described in Section 4.7.1.
2. The software device driver reads the HICR register and checks that the enable bit is set.
3. The software device driver writes the relevant command block into the shared RAM area.
4. The software device driver sets the Command bit in the control register. Setting this bit causes an
interrupt to management.
5. The software device driver polls the Control register until the Command bit is cleared by hardware.
6. When the MMS is done with the command, it clears the Command bit (if the MMS should reply with
a data, it should clear the bit only after the data is in the RAM area where the software device driver
can read it).
7. If the software device driver reads the Control register and the SV bit is set, it means that there is
a valid status of the last command in the RAM. If the SV is not set it means that the command has
failed with no status in the RAM.
8.23.2 HOST Interface Control Register - HICR (0x8F00; RW)
Field Bit(s) Initial Value Description
En (RO) 0 0b
Enable.
When set, it indicates that a RAM area is provided for software device driver
accesses.
This bit is read only for the software device driver.
C10b
Command.
The software device driver sets this bit when it has finished putting a
command block in the management internal DATA RAM. This bit should be
cleared by the firmware after the command’s processing completes.
SV (RO) 2 0b
Status Valid.
Indicates that there is a valid status in CSR area that the software device
driver can read.
1b = status valid.
0b = status not valid.
The value of the bit is valid only when the C bit is cleared.
Only the software device driver reads this bit.
Reserved 3 0b Reserved.
Reserved 6:4 0x0 Reserved.
FWR 7 0b
Firmware Reset.
When set by the host, it indicates that the hardware needs to assert a
firmware reset.
This bit is meaningful only when in the non-secured mode.
Reserved 8 0b Reserved.
Memory Base
Enable (RO)
90b
Enable host access to memory base register. This bit is set by the firmware
and is read only to the software device driver.
Reserved 31:10 0x0
Reserved.
Write 0x9, ignore on read.