Data Sheet

Ethernet Controller I210 — Programming Interface
532
Initial value:
Reset - The registers are cleared on LAN_PWR_GOOD only.
Note: These registers should be written in network order.
8.22.10 Manageability MAC Address Low - MMAL (0x5910 + 8*n [n=
0...3]; RW)
Where “n” is the exact unicast/multicast address entry, equal to 0...3.
These registers contain the lower bits of the 48-bit Ethernet address. The MMAL registers are written by
the MC and are not accessible to the host for writing. The registers are used to filter manageability
packets. See Section 10.3.
Reset - The MMAL registers are cleared on LAN_PWR_GOOD only. The initial values for this register can
be loaded from the Flash after power-up reset.
Note: The MMAL.MMAL field should be written in network order.
8.22.11 Manageability MAC Address High - MMAH (0x5914 + 8*n
[n=0...3]; RW)
Where “n” is the exact unicast/multicast address entry, equal to 0...3.
Field Bit(s) Initial Value
1
1. The initial values for these registers can be loaded from the Flash after power-up reset. The registers are written by the MC and
not accessible to the host for writing.
Description
IP_ADDR 4 bytes 31:0 X
4 bytes of IP (v6 or v4) address.
i mod 4 = 0 to bytes 1 - 4.
i mod 4 = 1 to bytes 5 - 8.
i mod 4 = 0 to bytes 9 - 12.
i mod 4 = 0 to bytes 13 - 16.
where i div 4 is the index of IP address (0...3).
Field Bit(s) Initial Value
1
1. The initial values for these registers can be loaded from the Flash after power-up reset. The registers are written by the MC and
not accessible to the host for writing.
Description
MMAL 31:0 X
Manageability MAC Address Low. The lower 32 bits of the 48 bit Ethernet
address.
Field Bit(s) Initial Value
1
1. The initial values for these registers can be loaded from the Flash after power-up reset. The registers are written by the MC and
not accessible to the host for writing.
Description
MMAH 15:0 X
Manageability MAC Address High.
The upper 16 bits of the 48 bit Ethernet address.
Reserved 31:16 0x0
Reserved.
Write 0x0, ignore on read.