Data Sheet

Programming Interface — Ethernet Controller I210
525
KEEP_PHY_LINK_UP 18 0b
1
Block PHY reset and power state changes.
When this bit is set, the PHY reset and power state changes do not effect the
PHY, This bit can not be written to unless the Keep_PHY_Link_Up_En Flash bit is
set.
Reserved 19 0b Reserved.
Reserved 22:20 0b
Reserved.
Write 0b, ignore on read.
EN_XSUM_FILTER 23 0b
1
Enable Checksum Filtering to MNG.
When this bit is set, only packets that pass L3and L4 checksums are sent to the
manageability block.
EN_IPv4_FILTER 24 0b
1
Enable IPv4 address Filters.
When set, the last 128 bits of the MIPAF register are used to store 4 IPv4
addresses for IPv4 filtering. When cleared, these bits store a single IPv6 filter.
FIXED_NET_TYPE 25 0b
1
Fixed Net Type.
If set, only packets matching the net type defined by the NET_TYPE field passes
to manageability. Otherwise, both tagged and un-tagged packets can be
forwarded to the manageability engine.
NET_TYPE 26 0b
1
Net Type.
0b = Pass only un-tagged packets.
1b = Pass only VLAN tagged packets.
Valid only if FIXED_NET_TYPE is set.
Reserved 27 0b
Reserved.
Write 0b, ignore on read.
EN_BMC2OS (RO) 28 0b
1
Enable MC-to-OS and OS-to-MC Traffic.
0b = The MC cannot communicate with the operating system.
1b = The MC can communicate with the operating system.
When cleared, the MC traffic is not forwarded to the operating system, even if
the host is the MAC.
The address filter and VLANs (RAH/L, MTA, VFTA and VLVF registers) indicate
that it should.
When cleared, the operating system traffic is not forwarded to the MC even if
the decision filters indicates it should. This bit does not impact the MC-to-
network traffic.
Notes:
1. Initial value loaded according to value of port n traffic types field in the
Flash(refer to Section 6.7.7.2).
2. Bit reflects the internal management Aux register bit.
Field Bit(s) Initial Value Description