Data Sheet

Ethernet Controller I210 — Programming Interface
522
8.21.18.2 Flex Filter 0 - Example
8.21.19 Flexible Host Filter Table Extended Registers - FHFT_EXT
(0x9A00 + 4*n [n=0...255]; RW)
Each of the four additional Flexible Host Filters table extended registers (FHFT_EXT) contains a 128
byte pattern and a corresponding 128-bit mask array. If enabled, the first 128 bytes of the received
packet are compared against the non-masked bytes in the FHFT_EXT register. The layout and access
rules of this table are the same as in FHFT.
8.22 Management Register Descriptions
All management registers are controlled by the remote MC for both read and write. Host accesses to
the management registers are blocked for write. The attributes for the fields in this section refer to the
MC access rights.
Note: All the registers described in this section can get their default values from the Flash when
manageability pass through works in legacy SMBus mode. The only exception being the
MANC register where part of the bits are masked. The specific MANC bits that can be loaded
from the Flash are indicated in the register description.
8.22.1 Management VLAN TAG Value - MAVTV (0x5010 +4*n [n=0...7];
RW)
Where “n” is the VLAN filter serial number, equal to 0,1...7.
Field Dword Address Bit(s) Initial Value
Filter 0 DW0 0 0x9000 31:0 X
Filter 0 DW1 1 0x9004 31:0 X
Filter 0 Mask[7:0] 2 0x9008 7:0 X
Reserved 3 0x900C 31:0 X
Filter 0 DW2 4 0x9010 31:0 X
…
Filter 0 DW30 60 0x90F0 31:0 X
Filter 0 DW31 61 0x90F4 31:0 X
Filter 0
Mask[127:120]
62 0x90F8 7:0 X
Length 63 0x90FC 7:0 X
Filter 0 Queueing 63 0x90FC 31:8 X
Field Bit(s) Initial Value Description
bit vector 31:0 X The details of the bit vector are described in Tabl e 8-2 4 .
Field Bit(s) Initial Value Description
VID 11:0 0x0
Contains the VLAN ID that should be compared with the incoming packet if
the corresponding bit in MDEF is set.
Reserved 31:12 0x0
Reserved.
Write 0x0, ignore on read