Data Sheet

Ethernet Controller I210 —Interconnects
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3.1.7.5 Partial Read and Write Requests
3.1.7.5.1 Partial Memory Accesses
The I210 has limited support of read/write requests with only part of the byte enable bits set:
• Partial writes with at least one byte enabled should not be used. If used, the results are
unexpected, either the byte enable request is honored or the entire Dword is written.
• Zero-length writes has no internal impact (nothing written, no effect such as clear-by-write). The
transaction is treated as a successful operation (no error event).
• Partial reads with at least one byte enabled are handled as a full read. Any side effect of the full
read (such as clear by read) is also applicable to partial reads.
• Zero-length reads generate a completion, but the register is not accessed and undefined data is
returned.
The I210 does not generate an error indication in response to any of the above events.
3.1.7.5.2 Partial I/O Accesses
• Partial access on address
— A write access is discarded
— A read access returns 0xFFFF
• Partial access on data, where the address access was correct
— A write access is discarded
— A read access performs the read
3.1.7.6 Error Pollution
Error pollution can occur if error conditions for a given transaction are not isolated on the error's first
occurrence. If the physical layer detects and reports a receiver error, to avoid having this error
propagate and cause subsequent errors at upper layers, the same packet is not signaled at the data
link or transaction layers.
Similarly, when the data link layer detects an error, subsequent errors that occur for the same packet
are not signaled at the transaction layer.
3.1.7.7 Completion with Unsuccessful Completion Status
A completion with unsuccessful completion status is dropped and not delivered to its destination. An
interrupt is generated to indicate unsuccessful completion.
3.1.7.8 Error Reporting Changes
The Rev. 1.1 specification defines two changes to advanced error reporting. A new Role-Based Error
Reporting bit in the Device Capabilities register is set to 1b to indicate that these changes are
supported by the I210. These changes are:
1. Setting the SERR# Enable bit in the PCI Command register also enables UR reporting (in the same
manner that the SERR# Enable bit enables reporting of correctable and uncorrectable errors). In
other words, the SERR# Enable bit overrides the UR Error Reporting Enable bit in the PCIe Device
Control register.