Data Sheet

Programming Interface — Ethernet Controller I210
509
8.21 Wake Up Control Register Descriptions
8.21.1 Wake Up Control Register - WUC (0x5800; R/W)
The PME_En and PME_Status bits of this register are reset when LAN_PWR_GOOD is 0b. When
AUX_PWR = 0b, these register bits also reset by de-asserting PE_RST_N and during a D3 to D0
transition.
Field Bit(s) Initial Value Description
APME 0 0b
1
1. Loaded from the Flash.
Advance Power Management Enable.
If set to 1b, APM Wakeup is enabled.
If this bit is set and the APMPME bit is cleared, reception of a magic packet asserts the
WUS.MAG bit but does not assert a PME.
Note: This bit is reset only on power-on reset but its value is auto-loaded from NVM on
PCIe reset.
PME_En 1 0b
PME_En.
This read/write bit is used by the software device driver to enable generation of a PME
event without writing to the Power Management Control / Status Register (PMCSR) in
the PCIe configuration space.
Note: This bit reflects the value of the PMCSR.PME_En bit when the bit in the PMCSR
register is modified. However, when the value of WUC.PME_En bit is modified by
software device driver, the value is not reflected in the PMCSR.PME_En bit.
Note: This bit is reset only on power-on reset When the AUX_PWR = 0b bit is also
reset on de-assertion of PE_RST_N and during D3 to D0 transition.
PME_Status (R/
W1C)
20b
PME_Status.
This bit is set when the I210
receives a wakeup event. It is the same as the PME_Status
bit in the Power Management Control / Status Register (PMCSR). Writing a 1b to this bit
clears also the PME_Status bit in the PMCSR.
Note: This bit is reset only on power-on reset When the AUX_PWR = 0b bit is also
reset on de-assertion of PE_RST_N and during D3 to D0 transition.
APMPME 3 0b
1
Assert PME On APM Wakeup.
If set to 1b, the I210 sets the PME_Status bit in the Power Management Control / Status
Register (PMCSR) and asserts PE_WAKE_N and sends a PM_PME PCIe message when
APM Wakeup is enabled (WUC.APME = 1b) and the I210 receives a matching Magic
Packet.
Notes:
1. When WUC.APMPME is set PE_WAKE_N is asserted and a PM_PME message is sent
even if PMCSR.PME_En is cleared.
2. This bit is reset only on power-on reset but its value is auto-loaded from NVM on
SW reset.
PPROXYE 4 0b
Port Proxying Enable.
When set to 1b Proxying of packets is enabled when device is in D3 low power state.
Note: Proxy information and requirements is passed by the software device driver to
firmware via the shared RAM host interface (refer to Section 10.8, Section 8.23
and Section 10.8.2.4.5).
EN_APM_D0 5 0b
1
Enable APM wake on D0.
0b = Enable APM wake only when function is in D3 and WUC.APME is set to 1b.
1b = Always enable APM wake when WUC.APME is set to 1b.
Note: This bit is reset on power on reset only.
Reserved 31:6 0x0
Reserved.
Write 0x0, ignore on read.