Data Sheet

Interconnects—Ethernet Controller I210
49
3.1.6.3 Polarity Inversion
If polarity inversion is detected, the receiver must invert the received data.
During the training sequence, the receiver looks at Symbols 6-15 of TS1 and TS2 as the indicator of
lane polarity inversion (D+ and D- are swapped). If lane polarity inversion occurs, the TS1 Symbols 6-
15 received are D21.5 as opposed to the expected D10.2. Similarly, if lane polarity inversion occurs,
Symbols 6-15 of the TS2 ordered set are D26.5 as opposed to the expected D5.2. This provides clear
indication of lane polarity inversion.
3.1.6.4 L0s Exit latency
The number of FTS sequences (N_FTS) sent during L1 exit, can be loaded from the Flash.
3.1.6.5 Reset
The PCIe PHY can supply a core reset to the I210. The reset can be caused by three sources:
1. Upstream move to hot reset - Inband Mechanism (LTSSM).
2. Recovery failure (LTSSM returns to detect).
3. Upstream component moves to disable.
3.1.6.6 Scrambler Disable
The scrambler/de-scrambler functionality in the I210 can be disabled by either one of the two
connected devices according to the PCIe specification.
3.1.7 Error Events and Error Reporting
3.1.7.1 Mechanism in General
PCIe defines two error reporting paradigms: the baseline capability and the Advanced Error Reporting
(AER) capability. The baseline error reporting capabilities are required of all PCIe devices and define the
minimum error reporting requirements. The AER capability is defined for more robust error reporting
and is implemented with a specific PCIe capability structure.
Both mechanisms are supported by the I210.
Also, the SERR# Enable and the Parity Error bits from the Legacy Command register take part in the
error reporting and logging mechanism.
3.1.7.2 Error Events
Table 3-12 lists the error events identified by the I210 and the response in terms of logging, reporting,
and actions taken. Consult the PCIe specification for the effect on the PCI Status register.