Data Sheet

Programming Interface — Ethernet Controller I210
487
8.18.2 Alignment Error Count - ALGNERRC (0x4004; RC)
Counts the number of receive packets with alignment errors (the packet is not an integer number of
bytes in length). In order for a packet to be counted in this register, it must pass address filtering and
must be 64 bytes or greater (from <Destination Address> through <CRC>, inclusive) in length. If
receives are not enabled, then this register does not increment. This register is valid only in MII mode
during 10/100 Mb/s operation.
8.18.3 Symbol Error Count - SYMERRS (0x4008; RC)
Counts the number of symbol errors between reads. The count increases for every bad symbol
received, whether or not a packet is currently being received and whether or not the link is up. When
working in SerDes/SGMII/1000BASE-KX mode these statistics can be read from the SCVPC register.
8.18.4 RX Error Count - RXERRC (0x400C; RC)
Counts the number of packets received in which RX_ER was asserted by the PHY. In order for a packet
to be counted in this register, it must pass address filtering and must be 64 bytes or greater (from
<Destination Address> through <CRC>, inclusive) in length. If receives are not enabled, then this
register does not increment.
This register is not available in SerDes/SGMII/1000BASE-KX modes.
8.18.5 Missed Packets Count - MPC (0x4010; RC)
Counts the number of missed packets. Packets are missed when the receive FIFO has insufficient space
to store the incoming packet. This can be caused because of too few buffers allocated, or because there
is insufficient bandwidth on the PCI bus. Events setting this counter causes ICR.Rx Miss, the Receiver
Overrun interrupt, to be set. This register does not increment if receives are not enabled.
These packets are also counted in the Total Packets Received register as well as in Total Octets
Received register.
Field Bit(s) Initial Value Description
AEC 31:0 0x0 Alignment Error Count.
Field Bit(s) Initial Value Description
SYMERRS 31:0 0x0 Symbol Error Count.
Field Bit(s) Initial Value Description
RXEC 31:0 0x0 Rx Error Count
Field Bit(s) Initial Value Description
MPC 31:0 0x0 Missed Packets Count.