Data Sheet

Ethernet Controller I210 — Programming Interface
486
8.18 Statistics Register Descriptions
All Statistics registers reset when read. In addition, they stick at 0xFFFF_FFFF when the maximum
value is reached.
For the receive statistics it should be noted that a packet is indicated as received if it passes the I210's
filters and is placed into the packet buffer memory. A packet does not have to be transferred to host
memory in order to be counted as received.
Due to divergent paths between interrupt-generation and logging of relevant statistics counts, it might
be possible to generate an interrupt to the system for a noteworthy event prior to the associated
statistics count actually being incremented. This is extremely unlikely due to expected delays
associated with the system interrupt-collection and ISR delay, but might be observed as an interrupt
for which statistics values do not quite make sense. Hardware guarantees that any event noteworthy of
inclusion in a statistics count is reflected in the appropriate count within 1 s; a small time-delay prior
to a read of statistics might be necessary to avoid the potential for receiving an interrupt and observing
an inconsistent statistics count as part of the ISR.
8.18.1 CRC Error Count - CRCERRS (0x4000; RC)
Counts the number of receive packets with CRC errors. In order for a packet to be counted in this
register, it must pass address filtering and must be 64 bytes or greater (from <Destination Address>
through <CRC>, inclusively) in length. If receives are not enabled, then this register does not
increment.
DATA_OUT 10 0b
I
2
C_DATA.
While in bit-bang mode and when the DATA_OE_N field is zero, controls the value
driven on the I2C_DATA pad.
DATA_OE_N 11 0b
I
2
C_DATA_OE_N.
While in bit-bang mode, controls the direction of the I2C_DATA pad.
0b = Pad is output.
1b = Pad is input.
DATA_IN (RO) 12 X
I
2
C_DATA_IN.
Reflects the value of the I2C_DATA pad. While in bit-bang mode when the
DATA_OE_N field is zero, this field reflects the value set in the DATA_OUT field.
CLK_OE_N 13 0b
I
2
C Clock Output Enable.
While in bit-bang mode, controls the direction of the I2C_CLK pad.
0b = Pad is output.
1b = Pad is input.
CLK_IN (RO) 14 X
I
2
C Clock In Value.
Reflects the value of the I2C_CLK pad. While in bit-bang mode when the CLK_OE_N
field is zero, this field reflects the value set in the CLK_OUT field.
clk_stretch_dis 15 0b
0b = Enable slave clock stretching support in I
2
C access.
1b = Disable clock stretching support in I
2
C access.
Reserved 31:16 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
CEC 31:0 0x0 CRC Error Count.
Field Bit(s) Initial Value Description