Data Sheet

Programming Interface — Ethernet Controller I210
485
8.17.9 SFP I2C Parameters - I2CPARAMS (0x102C; R/W)
This register is used to set the parameters for the I
2
C access to the SFP module and to enable bit-
banging access to the I
2
C interface, when either the CTRL_EXT.I2C Enabled or the CTRL_EXT.I2C over
SDP Enabled bit is set to 1b. Prior to write accessing this register, the I
2
C semaphore ownership must
be taken, and released at the end of the access sequence.
Field Bit(s) Initial Value Description
DATA 15:0 X
Data.
In a Write command, software places the data bits and then the MAC shifts them out
to the I
2
C bus. In a Read command, the MAC reads these bits serially from the I
2
C bus
and then software reads them from this location.
Note: This field is read in byte order and not in word order.
REGADD 23:16 0x0
I
2
C Register Address.
For example, register 0, 1, 2... 255.
PHYADD 26:24 0x0
Device Address Bits 3 -1.
The actual address used is b{1010, PHYADD[2:0], 0}.
On power up, FW loads a default value from the PHY_ADD field in NVM Initialization
Control 4 (word 0x13).
OP 27 0b
Op-code.
0b = I
2
C write.
1b = I
2
C read.
Reset 28 0b
Reset Sequence.
If set, sends a reset sequence before the actual read or write.
This bit is self clearing.
A reset sequence is defined as nine consecutive stop conditions.
R290b
Ready Bit.
Set to 1b by the I210 at the end of the I
2
C transaction. For example, indicates a read
or write completed.
Reset by a software write of a command.
I300b
Interrupt Enable.
When set to 1b by software, it causes an interrupt to be asserted to indicate the end
of an I
2
C cycle (ICR.MDAC).
E310b
Error.
This bit set is to 1b by hardware when it fails to complete an I
2
C read. Reset by a
software write of a command.
Note: Bit is valid only when Ready bit is set.
Field Bit(s) Initial Value Description
Write Time 4:0 110b
Write Time.
Defines the delay between a write access and the next access. The value is in
milliseconds. A value of zero is not valid.
Read Time 7:5 010b
Read Time.
Defines the delay between a read access and the next access. The value is in
microseconds. A value of Zero is not valid
I2CBB_EN 8 0b
I
2
C Bit-bang Enable.
If set, the I
2
C_CLK and I
2
C_DATA lines are controlled via the CLK, DATA and
DATA_OE_N fields of this register. Otherwise, they are controlled by the hardware
machine activated via the I2CCMD or MDIC registers.
CLK 9 0b
I
2
C Clock.
While in bit-bang mode, controls the value driven on the I2C_CLK pad.