Data Sheet

Ethernet Controller I210 —Interconnects

The following DLLPs are supported by the I210 as a transmitter:

Note: UpdateFC-Cpl is not sent because of the infinite FC-Cpl allocation.

3.1.5.3 Transmit EDB Nullifying

If re-train is necessary, there is a need to guarantee that no abrupt termination of the Tx packet

happens. For this reason, early termination of the transmitted packet is possible. This is done by

appending an End Bad Symbol (EDB) to the packet.

3.1.6 Physical Layer

3.1.6.1 Link Speed

• The I210 supports only 2.5GT/s link speeds.

The I210 does not initiate a hardware autonomous speed change and as a result the Hardware

Autonomous Speed Disable bit in the PCIe Link Control 2 register is hardwired to 0b.

The I210 supports entering compliance mode at the speed indicated in the Target Link Speed field in

the PCIe Link Control 2 register. Compliance mode functionality is controlled via the Enter Compliance

bit in the PCIe Link Control 2 register.

3.1.6.2 Link Width

The I210 supports a maximum link width of x1.

During link configuration, the platform and the I210 negotiate on a common link width. The link width

must be x1.

Table 3-11. DLLPs Initiated by the I210

DLLP type Remarks

ACK

NAK

PM_Enter_L1

PM_Enter_L23

PM_Active_State_Request_L1

InitFC1-P Virtual Channel 0 only

InitFC1-NP Virtual Channel 0 only

InitFC1-Cpl Virtual Channel 0 only

InitFC2-P Virtual Channel 0 only

InitFC2-NP Virtual Channel 0 only

InitFC2-Cpl Virtual Channel 0 only

UpdateFC-P Virtual Channel 0 only

UpdateFC-NP Virtual Channel 0 only