Data Sheet
Programming Interface — Ethernet Controller I210
479
8.17.1 PCS Configuration - PCS_CFG (0x4200; R/W)
8.17.2 PCS Link Control - PCS_LCTL (0x4208; RW)
Field Bit(s) Initial Value Description
Reserved 2:0 0x0
Reserved.
Write 0x0, ignore on read.
PCS Enable 3 1b
PCS Enable.
Enables the PCS logic of the MAC. Should be set in SGMII, 1000BASE-KX and SerDes
mode for normal operation.
Clearing this bit disables Rx/Tx of both data and control codes. Use this to force link
down at the far end.
Reserved 29:4 0x0
Reserved.
Write 0x0, ignore on read.
PCS Isolate 30 0b
PCS Isolate.
Setting this bit isolates the PCS logic from the MAC's data path. PCS control codes are
still sent and received.
SRESET 31 0b
Soft Reset.
Setting this bit puts all modules within the MAC in reset except the Host Interface.
The Host Interface is reset via HRST. This bit is NOT self clearing; GMAC is in a reset
state until this bit is cleared.
Field Bit(s) Initial Value Description
FLV 0 0b
Forced Link Value.
This bit denotes the link condition when force link is set.
0b = Forced link down.
1b = Forced link up.
FSV 2:1 10b
Forced Speed Value.
These bits denote the speed when force speed and duplex (PCS_LCTL.FSD) bit is set.
This value is also used when AN is disabled or when in SerDes mode.
00b = 10 Mb/s (SGMII).
01b = 100 Mb/s (SGMII).
10b = 1000 Mb/s (SerDes/SGMII/1000BASE-KX).
11b = Reserved.
FDV 3 1b
Forced Duplex Value.
This bit denotes the duplex mode when force speed and duplex (PCS_LCTL.FSD) bit is
set. This value is also used when AN is disabled or when in SerDes mode.
1b = Full duplex (SerDes/SGMII/1000BASE-KX).
0b = Half duplex (SGMII).
FSD 4 0b
Force Speed and Duplex.
If this bit is set, then speed and duplex mode is forced to forced speed value and
forced duplex value, respectively. Otherwise, speed and duplex mode are decided by
internal AN/SYNC state machines.
Force Link 5 0b
Force Link.
If this bit is set, then the internal LINK_OK variable is forced to forced link value (bit 0
of this register).
Otherwise, LINK_OK is decided by internal AN/SYNC state machines.
LINK LATCH
LOW (LL)
60b
Link Latch Low Enable.
If this bit is set, then link OK going LOW (negative edge) is latched until a processor
read. Afterwards, link OK is continuously updated until link OK again goes LOW
(negative edge is seen).