Data Sheet

Ethernet Controller I210 — Programming Interface
478
8.16.2 Time Sync Interrupt Mask Register - TSIM (0xB674; RW)
8.17 PCS Register Descriptions
These registers are used to configure the SerDes, SGMII and 1000BASE-KX PCS logic. Usage of these
registers is described in Section 3.7.4.1 and Section 3.7.4.3.
AUTT1 6 0b
Auxiliary Timestamp 1 Taken.
Set when new timestamp is loaded into AUXSTMP 1 (auxiliary timestamp
1) register.
TADJ 7 0b
Time Adjust Done.
Set when time adjust-to-SYSTIM completes.
Reserved 31:8 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
SYS WARP 0 0b
SYSTIM Warp Around Mask.
0b = No interrupt generated when TSICR.SWARP is set.
1b= Interrupt generated when TSICR.SWARP is set.
TXTS 1 0b
Transmit Timestamp Mask.
0b = No interrupt generated when TSICR.TXTS is set.
1b= Interrupt generated when TSICR.TXTS is set.
RXTS 2 0b
Receive Timestamp Mask.
0b = No interrupt generated when TSICR.RXTS is set.
1b= Interrupt generated when TSICR.RXTS is set.
TT0 3 0b
Target time 0 Trigger Mask.
0b = No interrupt generated when TSICR.TT0 is set.
1b= Interrupt generated when TSICR.TT0 is set.
TT1 4 0b
Target time 1 Trigger Mask.
0b = No interrupt generated when TSICR.TT1 is set.
1b= Interrupt generated when TSICR.TT1 is set.
AUTT0 5 0b
Auxiliary Timestamp 0 Taken Mask.
0b = No interrupt generated when TSICR.AUTT0 is set.
1b= Interrupt generated when TSICR.AUTT0 is set.
AUTT1 6 0b
Auxiliary Timestamp 1 Taken Mask.
0b = No interrupt generated when TSICR.AUTT1 is set.
1b = Interrupt generated when TSICR.AUTT1 is set.
TADJ 7 0b
Time Adjust 0 Done Mask.
0b = No interrupt generated when TSICR.TADJ is set.
1b = Interrupt generated when TSICR.TADJ is set.
Reserved 31:8 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description