Data Sheet

Programming Interface — Ethernet Controller I210
477
8.16 Time Sync Interrupt Registers
8.16.1 Time Sync Interrupt Cause Register - TSICR (0xB66C; RC/W1C)
Note: Once ICR.Time_Sync is set, the internal value of this register should be cleared by writing 1b
to all bits or cleared by a read to enable receiving an additional ICR.Time_Sync interrupt.
TS_SDP1_SEL 10:9 00b
SDP1 allocation to Tsync event – when TS_SDP1_EN is set, these bits select the
Tsync event that is routed to SDP1.
00b = Target time 0 is output on SDP1.
01b = Target time 1 is output on SDP1.
10b = Freq clock 0 is output on SDP1.
11b = Freq clock 1 is output on SDP1.
TS_SDP1_EN 11 0b When set indicates that SDP1 is assigned to Tsync.
TS_SDP2_SEL 13:12 00b
SDP2 allocation to Tsync event – when TS_SDP2_EN is set, these bits select the
Tsync event that is routed to SDP2.
00b = Target time 0 is output on SDP2.
01b = Target time 1 is output on SDP2.
10b = Freq clock 0 is output on SDP2.
11b = Freq clock 1 is output on SDP2.
TS_SDP2_EN 14 0b When set indicates that SDP2 is assigned to Tsync.
TS_SDP3_SEL 16:15 00b
SDP3 allocation to Tsync event – when TS_SDP3_EN is set, these bits select the
Tsync event that is routed to SDP3.
00b = Target time 0 is output on SDP3.
01b = Target time 1 is output on SDP3.
10b = Freq clock 0 is output on SDP3.
11b = Freq clock 1 is output on SDP3.
TS_SDP3_EN 17 0b When set indicates that SDP3 is assigned to Tsync.
Reserved 31:18 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
SYS WARP 0 0b
SYSTIM Warp around.
Set when SYSTIML This event should happen every second.
TXTS 1 0b
Transmit Timestamp.
Set when new timestamp is loaded into TXSTMP register.
RXTS 2 0b
Receive Timestamp.
Set when new timestamp is loaded into RXSTMP register.
TT0 3 0b
Tar g et Tim e 0 Trig ger.
Set when target time 0 (TRGTTIML/H0) trigger occurs. This interrupt is
enabled only if the EN_TT0 flag in the TSAUXC register is set. Note that this
interrupt cause is set also by CLK0 output which is based on TRGTTIM0.
TT1 4 0b
Tar g et Tim e 1 Trig ger.
Set when target time 1 (TRGTTIML/H1) trigger occurs. This interrupt is
enabled only if the EN_TT1 flag in the TSAUXC register is set. Note that this
interrupt cause is set also by CLK1 output which is based on TRGTTIM1.
AUTT0 5 0b
Auxiliary Timestamp 0 Taken.
Set when new timestamp is loaded into AUXSTMP 0 (auxiliary timestamp
0) register.
Field Bit(s) Initial Value Description