Data Sheet
Ethernet Controller I210 — Programming Interface
476
8.15.23 Auxiliary Time Stamp 1 Register High - AUXSTMPH1 (0xB668;
RO)
Reading this register releases the value stored in AUXSTMPH/L1 and enables timestamping of the next
value.
8.15.24 Time Sync RX Configuration - TSYNCRXCFG (0x5F50; R/W)
8.15.25 Time Sync SDP Configuration Register - TSSDP (0x003C; R/W)
This register defines the assignment of SDP pins to the time sync auxiliary capabilities.
Field Bit(s) Initial Value Description
TSTH 31:0 0x0 Auxiliary Time Stamp 1 MSB value (defined in second units).
Field Bit(s) Initial Value Description
CTRLT 7:0 0x0 V1 control to timestamp.
MSGT 15:8 0x0 V2 Message Type to timestamp.
Reserved 31:16 0x0
Reserved.
Write 0x0, ignore on read.
Field Bit(s) Initial Value Description
AUX0_SDP_SEL 1:0 00b
Select one of the SDPs to serve as the trigger for auxiliary time stamp 0
(AUXSTMPL0 and AUXSTMPH0 registers).
00b = SDP0 is assigned.
01b = SDP1 is assigned.
10b = SDP2 is assigned.
11b = SDP3 is assigned.
AUX0_TS_SDP_EN 2 0b
When set indicates that one of the SDPs can be used as an external trigger to
Aux timestamp 0 (note that if this bit is set to one of the SDP pins, the
corresponding pin should be configured to input mode using SPD_DIR).
AUX1_SDP_SEL 4:3 00b
Select one of the SDPs to serve as the trigger for auxiliary time stamp 1 (in
AUXSTMPL1 and AUXSTMPH1 registers).
00b = SDP0 is assigned.
01b = SDP1 is assigned.
10b = SDP2 is assigned.
11b = SDP3 is assigned.
AUX1_TS_SDP_EN 5 0b
When set indicates that one of the SDPs can be used as an external trigger to
Aux timestamp 1 (note that if this bit is set to one of the SDP pins, the
corresponding pin should be configured to input mode using SPD_DIR).
TS_SDP0_SEL 7:6 00b
SDP0 allocation to Tsync event – when TS_SDP0_EN is set, these bits select the
Tsync event that is routed to SDP0.
00b = Target time 0 is output on SDP0.
01b = Target time 1 is output on SDP0.
10b = Freq clock 0 is output on SDP0.
11b = Freq clock 1 is output on SDP0.
TS_SDP0_EN 8 0b When set indicates that SDP0 is assigned to Tsync.