Data Sheet

Programming Interface — Ethernet Controller I210
473
8.15.13 TimeSync Auxiliary Control Register - TSAUXC (0xB640; RW)
Field Bit(s) Initial Value Description
EN_TT0 0 0b
Enable target time 0.
Enable bit is set by software to 1b, to enable pulse or level change generation as a
function of the TSAUXC.PLSG bit.
EN_TT1 1 0b
Enable target time 1.
Enable bit is set by software to 1b, to enable a level change.
EN_CLK0 2 0b
Enable Configurable Frequency Clock 0.
Clock is generated according to frequency defined in the FREQOUT0 register on the
SDP pin (0 to 3) that has both:
1. TSSDP.TS_SDPx_SEL field with a value of 10b.
2. TSSDP.TS_SDPx_EN value of 1b.
SAMP_AUT0 3 0b
When setting the SAMP_AUT0 flag the SYSTIML/H registers are latched to the
AUXSTMPL0/ AUXSTMPH0 registers. Then the SAMP_AUT0 flag is auto-cleared by the
hardware.
Reserved 4 0b Reserved.
EN_CLK1 5 0b
Enable Configurable Frequency Clock 1.
Clock is generated according to frequency defined in the FREQOUT1 register on the
SDP pin (0 to 3) that has both:
1. TSSDP.TS_SDPx_SEL field with a value of 11b.
2. TSSDP.TS_SDPx_EN value of 1b.
SAMP_AUT1 6 0b
When setting the SAMP_AUT1 flag the SYSTIML/H registers are latched to the
AUXSTMPL1/ AUXSTMPH1 registers. Then the SAMP_AUT1 flag is auto-cleared by the
hardware.
Reserved 7 0b Reserved.
EN_TS0 8 0b
Enable hardware timestamp 0.
Enable Timestamping occurrence of change in SDP pin into the AUXSTMPL0 and
AUXSTMPH0 registers.
SDP pin (0 to 3) is selected for time stamping, if the SDP pin is selected via the
TSSDP.AUX0_SDP_SEL field and the TSSDP.AUX0_TS_SDP_EN bit is set to 1b.
AUTT0 9 0b
Auxiliary Timestamp Taken.
Cleared when read from auxiliary timestamp 0 occurred.
EN_TS1 10 0b
Enable Hardware Timestamp 1.
Enable timestamping occurrence of change in SDP pin into the AUXSTMPL1 and
AUXSTMPH1 registers.
SDP pin (0 to 3) is selected for time stamping, if the SDP pin is selected via the
TSSDP.AUX1_SDP_SEL field and the TSSDP.AUX1_TS_SDP_EN bit is set to 1b.
AUTT1 11 0b
Auxiliary Timestamp Taken.
Cleared when read from auxiliary timestamp 1 occurred.
Reserved 16:12 0x0
Reserved.
Write 0x0, ignore on read.
PLSG 17 0b
Use Target Time 0 to generate start of pulse and Target Time 1 to generate end of
pulse. SDP pin selected to drive pulse or level change is set according to the
TSSDP.TS_SDPx_SEL field with a value of 00b and TSSDP.TS_SDPx_EN bit with a
value of 1b.
0b = Target Time 0 generates change in SDP level.
1b = Target time 0 generates start of pulse on SDP pin.
Note: Pulse or level change is generated when TSAUXC.EN_TT0 is set to 1b.